Abstract—Recent advances in process technology have resulted
in novel defect mechanisms making the test generation process
very challenging. In addition to complete opens and shorts that
can be represented via extreme defect resistance magnitudes,
partial resistive opens and shorts are also of concern in deeply
scaled CMOS technologies. For open defects with intermediate
defect magnitude values, it has been shown that multi-pattern
tests are necessary for defect exposure. We extend this approach
to short defects with intermediate defect magnitude values to
obtain a suite of multi-pattern tests for standard cell instances
that cover complete as well as partial intra-cell open and short
defects. A hierarchical scan-compatible SAT-based test generation
approach for full scan sequential circuits is then proposed that
allows such multi-pattern tests to be applied to the circuit via the
scan infrastructure. A key innovation is the combined use of shift
and capture operations along with launch-on-capture and launch-on-
shift scan based test application for increased defect coverage.
Resulting defect coverage improvements over conventional two-pattern
tests are demonstrated on ISCAS89 benchmark circuits.
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An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures
Traditional low cost scan based structural tests no longer suffice for delivering acceptable defect levels in many processor SOCs, especially those targeting low power applications. Expensive functional system level tests (SLTs) have become an additional and necessary final test screen. Efforts to eliminate or minimize the use of SLTs have focused on new fault models and improved test generation methods to improve the effectiveness of scan tests. In this paper we argue that given the limitations of scan timing tests, such an approach may not be sufficient to detect all the low voltage failures caused by circuit timing variability that appear to dominate SLT fallout. Instead, we propose an alternate approach for meaningful cost savings that adaptively avoids SLT tests for a subset of the manufactured parts. This is achieved by using parametric and scan tests results from earlier in the test flow to identify low delay variability parts that can avoid SLT with minimal impact on DPPM. Extensive SPICE simulations support the viability of our proposed approach. We also show that such an adaptive test flow is also very well suited to real time optimization during the using machine-learning techniques.
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- Award ID(s):
- 1910964
- PAR ID:
- 10355107
- Date Published:
- Journal Name:
- 2019 IEEE International Test Conference (ITC)
- Page Range / eLocation ID:
- 1 to 10
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
-
Accepted Manuscript1.0
- Conference Paper:
- https://doi.org/10.1109/ITC44170.2019.9000173
