Traditional low cost scan based structural tests no longer suffice for delivering acceptable defect levels in many processor SOCs, especially those targeting low power applications. Expensive functional system level tests (SLTs) have become an additional and necessary final test screen. Efforts to eliminate or minimize the use of SLTs have focused on new fault models and improved test generation methods to improve the effectiveness of scan tests. In this paper we argue that given the limitations of scan timing tests, such an approach may not be sufficient to detect all the low voltage failures caused by circuit timing variability that appear to dominate SLT fallout. Instead, we propose an alternate approach for meaningful cost savings that adaptively avoids SLT tests for a subset of the manufactured parts. This is achieved by using parametric and scan tests results from earlier in the test flow to identify low delay variability parts that can avoid SLT with minimal impact on DPPM. Extensive SPICE simulations support the viability of our proposed approach. We also show that such an adaptive test flow is also very well suited to real time optimization during the using machine-learning techniques.
Exploring the Mysteries of System-Level Test
Abstract—System-level test, or SLT, is an increasingly important
process step in today’s integrated circuit testing flows.
Broadly speaking, SLT aims at executing functional workloads
in operational modes. In this paper, we consolidate available
knowledge about what SLT is precisely and why it is used
despite its considerable costs and complexities. We discuss the
types or failures covered by SLT, and outline approaches to
quality assessment, test generation and root-cause diagnosis in
the context of SLT. Observing that the theoretical understanding
for all these questions has not yet reached the level of maturity
of the more conventional structural and functional test methods,
we outline new and promising directions for methodical developments
leveraging on recent findings from software engineering.
- Award ID(s):
- 1910964
- Publication Date:
- NSF-PAR ID:
- 10401355
- Journal Name:
- 2020 IEEE Asian Test Symposium
- Page Range or eLocation-ID:
- 1 to 6
- Sponsoring Org:
- National Science Foundation
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Accepted Manuscript1.0
- Publisher's Version of Record
- https://doi.org/10.1109/ATS49688.2020.9301557
