To exploit their charge transport properties in transistors, semiconducting carbon nanotubes must be assembled into aligned arrays comprised of individualized nanotubes at optimal packing densities. However, achieving this control on the wafer‐scale is challenging. Here, solution‐based shear in substrate‐wide, confined channels is investigated to deposit continuous films of well‐aligned, individualized, semiconducting nanotubes. Polymer‐wrapped nanotubes in organic ink are forced through sub‐mm tall channels, generating shear up to 10 000 s−1uniformly aligning nanotubes across substrates. The ink volume and concentration, channel height, and shear rate dependencies are elucidated. Optimized conditions enable alignment within a ±32° window, at 50 nanotubes µm−1, on 10 × 10 cm2substrates. Transistors (channel length of 1–5 µm) are fabricated parallel and perpendicular to the alignment. The parallel transistors perform with 7× faster charge carrier mobility (101 and 49 cm2V−1s−1assuming array and parallel‐plate capacitances, respectively) with high on/off ratio of 105. The spatial uniformity varies ±10% in density, ±2° in alignment, and ±7% in mobility. Deposition occurs within seconds per wafer, and further substrate scaling is viable. Compared to random networks, aligned nanotube films promise to be a superior platform for applications including sensors, flexible/stretchable electronics, and light emitting and harvesting devices.
Fabricating flexible electronics on plastic is often limited by the poor dimensional stability of polymer substrates. To mitigate, glass carriers are used during fabrication, but removing the plastic substrate from a carrier without damaging the electronics remains challenging. Here we utilize a large-area, high-throughput photonic lift-off (PLO) process to rapidly separate polymer films from rigid carriers. PLO uses a 150 µs pulse of broadband light from flashlamps to lift-off functional thin films from glass carrier substrates coated with a light absorber layer (LAL). Modeling indicates that the polymer/LAL interface reaches above 800 °C during PLO, but the top surface of the PI remains below 120 °C. An array of indium zinc oxide (IZO) thin-film transistors (TFTs) was fabricated on a polyimide substrate and photonically lifted off from the glass carrier. The TFT mobility was unchanged by PLO. The flexible TFTs were mechanically robust, with no reduction in mobility while flexed.
more » « less- NSF-PAR ID:
- 10363423
- Publisher / Repository:
- Nature Publishing Group
- Date Published:
- Journal Name:
- npj Flexible Electronics
- Volume:
- 6
- Issue:
- 1
- ISSN:
- 2397-4621
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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Abstract -
Over the two decades, amorphous oxide semiconductors (AOSs) and their thin film transistor (TFT) channel application have been intensely explored to realize high performance, transparent and flexible displays due to their high field effect mobility (μFE=5-20 cm2/Vs), visible range optical transparency, and low temperature processability (25-300 °C).[1-2] The metastable amorphous phase is to be maintained during operation by the addition of Zn and additional third cation species (e.g., Ga, Hf, or Al) as an amorphous phase stabilizer.[3-5] To limit TFT off-state currents, a thin channel layer (10-20 nm) was employed for InZnO (IZO)-based TFTs, or third cations were added to suppress carrier generations in the TFT channel. To resolve bias stress-induced instabilities in TFT performance, approaches to employ defect passivation layers or enhance channel/dielectric interfacial compatibility were demonstrated.[6-7] Metallization contact is also a dominating factor that determines the performance of TFTs. Particularly, it has been reported that high electrical contact resistance significantly sacrifices drain bias applied to the channel, which leads to undesirable power loss during TFT operation and issues for the measurement of TFT field effect mobilities. [2, 8] However, only a few reports that suggest strategies to enhance contact behaviors are available in the literature. Furthermore, the previous approaches (1) require an additional fabrication complexity due to the use of additional treatments at relatively harsh conditions such as UV, plasma, or high temperatures, and (2) may lead to adverse effects on the channel material attributed to the chemical incompatibility between dissimilar materials, and exposures to harsh environments. Therefore, a simple and easy but effective buffer strategy, which does not require any additional process complexities and not sacrifice chemical compatibility, needs to be established to mitigate the contact issues and therefore achieve high performance and low power consumption AOS TFTs. The present study aims to demonstrate an approach utilizing an interfacial buffer layer, which is compositionally homogeneous to the channel to better align work functions between channel and metallization without a significant fabrication complexity and harsh treatment conditions. Photoelectron spectroscopic measurements reveal that the conducting IZO buffer, of which the work function (Φ) is 4.37 eV, relaxes a relatively large Φ difference between channel IZO (Φ=4.81 eV) and Ti (Φ=4.2-4.3 eV) metallization. The buffer is found to lower the energy barrier for charge carriers at the source to reach the effective channel region near the dielectric. In addition, the higher carrier density of the buffer and favorable chemical compatibility with the channel (compositionally the same) further contribute to a significant reduction in specific contact resistance as much as more than 2.5 orders of magnitude. The improved contact and carrier supply performance from the source to the channel lead to an enhanced field effect mobility of up to 56.49 cm2/Vs and a threshold voltage of 1.18 V, compared to 13.41 cm2/Vs and 7.44 V of IZO TFTs without a buffer. The present work is unique in that an approach to lower the potential barrier between the source and the effective channel region (located near the channel/dielectric interface, behaving similar to a buried-channel MOSFET [9]) by introducing a contact buffer layer that enhances the field effect mobility and facilitates carrier supply from the source to the effective channel region.more » « less
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In recent years, oxide electronics has emerged as one of the most promising new technologies for a variety of electrical and optoelectronic applications, including next-generation displays, solar cells, batteries, and photodetectors. Oxide electronics have a lot of potential because of their high carrier mobilities and ability to be manufactured at low temperatures. However, the preponderance of oxide semiconductors is n-type oxides, limiting present applications to unipolar devices and stifling the development of oxide-based bipolar devices like p-n diodes and complementary metal-oxide–semiconductors. We have contributed to oxide electronics, particularly on transition metal oxide semiconductors of which the cations include In, Zn, Sn and Ga. We have integrated these oxide semiconductors into thin film transistors (TFTs) as active channel layer in light of the unique combination of electronic and optical properties such as high carrier mobility (5-10 cm2/Vs), optical transparency in the visible regime (>~90%) and mild thermal budget processing (200-400°C). In this study, we achieved four different results. The first result is that unlike several previous reports on oxide p-n junctions fabricated exploiting a thin film epitaxial growth technique (known as molecular beam epitaxy, MBE) or a high-powered laser beam process (known as pulsed laser deposition, PLD) that requires ultra-high vacuum conditions, a large amount of power, and is limited for large-area processing, we demonstrate oxide-based heterojunction p-n diodes that consist of sputter-synthesized p-SnOx and n-IGZO of which the manufacturing routes are in-line with current manufacturing requirements. The second result is that the synthesized p-SnOx films are devoid of metallic Sn phases (i.e., Sn0 state) with carrier density tuneability and high carrier mobility (> 2 cm2/Vs). The third result is that the charge blocking performance of the metallurgical junction is significantly enhanced by the engineering of trap/defect density of n-IGZO, which is identified using photoelectron microscopy and valence band measurements. The last result is that the resulting oxide-based p-n heterojunction exhibits a high rectification ratio greater than 103 at ±3 V (highest among the sputter-processed oxide junctions), a low saturation current of ~2×10-10 A, and a small turn-on voltage of ~0.5 V. The outcomes of the current study are expected to contribute to the development of p-type oxides and their industrial device applications such as p-n diodes of which the manufacturing routes are in-line with the current processing requirements.more » « less
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Abstract The lamination of a high‐capacitance ion gel dielectric layer onto semiconducting carbon nanotube (CNT) thin‐film transistors (TFTs) that are bottom‐gated with a low‐capacitance polymer dielectric layer drastically reduces the operating voltage of the devices resulting from the capacitive coupling effect between the two dielectric layers sandwiching the CNT channel. As the CNT channel has a network structure, only a compact area of ion gel is required to make the capacitive coupling effect viable, unlike the planar channels of previously reported transistors that required a substantially larger area of ion gel dielectric layer to induce the coupling effect. The capacitively coupled CNT TFTs possess superlative electrical characteristics such as high carrier mobilities (42.0 cm2(Vs)−1for holes and 59.1 cm2(Vs)−1for electrons), steep subthreshold swings (160 mV dec−1for holes and 100 mV dec−1for electrons), and low gate leakage currents (<1 nA). These devices can be further integrated to form complex logic circuits on flexible substrates with high mechanical resilience. The layered geometry of the device coupled with scalable solution‐based fabrication has significant potential for large‐scale flexible electronics.
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Flexible electronics with highly thermal stability and mechanical strength are highly needed in advanced transportation systems. Semiconducting single‐walled carbon nanotubes are one of the leading active materials for such thin film transistors because they are printable, flexible, thermally stable, and mechanically strong. Dielectrics with large capacitance are another major component, and polymer electrolytes are printed for flexible electronics, but they suffer from poor mechanical strength and low operating temperature. Here, a transparent, mechanically flexible, and thermally stable polyfluorinated electrolyte (PFE) is developed with high capacitance by curing printed polyfluorinated resin (PFR) and ionic liquid composite at high temperature. PFE inherits the mechanical flexibility and thermal stability from PFR. The immobilized ionic liquid inside the porous structures of PFE accounts for the high capacitance. With top‐gated PFE, fully printed electronically pure single‐chirality (6,5) single‐walled carbon nanotube (SWCNT) thin‐film transistors (TFTs) exhibit air stable, consistent, and reliable ambipolar characteristics with high transconductance (1 mS) and small subthreshold swing (<0.15 V dec−1) at low voltage in ambient air for p‐type and n‐type carriers, and >105ON/OFF current ratio for both carriers under low operation voltage.
