skip to main content
US FlagAn official website of the United States government
dot gov icon
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
https lock icon
Secure .gov websites use HTTPS
A lock ( lock ) or https:// means you've safely connected to the .gov website. Share sensitive information only on official, secure websites.

Explore Research Products in the PAR
It may take a few hours for recently added research products to appear in PAR search results.


Title: Compact Modeling and Design of Magneto-Electric Transistor Devices and Circuits
A Verilog-A based model for the magneto-electric field effect transistor (MEFET) device is implemented and a variety of logic functions based on this device are proposed. These models are used to capture energy consumption and delay per switching event and to benchmark the MEFET with respect to CMOS. Single-source MEFET devices can be used for conventional logic gates like NAND, NOR, inverter and buffer and more complex circuits like the full adder. The dual source MEFET is an enhanced version of the MEFET device which functions like a spin multiplexer (spin-MUXer). Circuits using MEFETs require fewer components than CMOS to generate the same logic operation. These devices display a high on-off ratio., unlike many magneto-electric devices., and they operate at very low voltages., resulting in lower switching energy. Benchmarking results show that these devices perform better in terms of energy and delay., for implementing more complex functions., than the basic logic gates.  more » « less
Award ID(s):
1740136
PAR ID:
10096464
Author(s) / Creator(s):
; ; ; ; ;
Date Published:
Journal Name:
2018 31st IEEE International System-on-Chip Conference (SOCC)
Page Range / eLocation ID:
146 to 151
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
More Like this
  1. ; ; (, 55th Annual Design Automation Conference)
    In this paper, we propose PIMA-Logic, as a novel Processing-in-Memory Architecture for highly flexible and efficient Logic computation. Insteadof integrating complex logic units in cost-sensitive memory, PIMA-Logic exploits a hardware-friendly approach to implement Boolean logic functions between operands either located in the same row or the same column within entire memory arrays. Furthermore, it can efficiently process more complex logic functions between multiple operands to further reduce the latency and power-hungry data movement. The proposed architecture is developed based on Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array and it can simultaneously work as a non-volatile memory and a reconfigurable in-memory logic. The device-to-architecture co-simulation results show that PIMA-Logic can achieve up to 56% and 31.6% improvements with respect to overall energy and delay on combinational logic benchmarks compared to recent Pinatubo architecture. We further implement an in-memory data encryption engine based on PIMA-Logic as a case study. With AES application, it shows 77.2% and 21% lower energy consumption compared to CMOS-ASIC and recent RIMPA implementation, respectively. 
    more » « less
  2. ; ; ; ; ; ; ; ; (, ACS Nano)
    Ambipolar dual-gate transistors based on low-dimensional materials, such as graphene, carbon nanotubes, black phosphorus, and certain transition metal dichalcogenides (TMDs), enable reconfigurable logic circuits with a suppressed off-state current. These circuits achieve the same logical output as complementary metal–oxide semiconductor (CMOS) with fewer transistors and offer greater flexibility in design. The primary challenge lies in the cascadability and power consumption of these logic gates with static CMOS-like connections. In this article, high-performance ambipolar dual-gate transistors based on tungsten diselenide (WSe2) are fabricated. A high on–off ratio of 108 and 106, a low off-state current of 100 to 300 fA, a negligible hysteresis, and an ideal subthreshold swing of 62 and 63 mV/dec are measured in the p- and n-type transport, respectively. We demonstrate cascadable and cascaded logic gates using ambipolar TMD transistors with minimal static power consumption, including inverters, XOR, NAND, NOR, and buffers made by cascaded inverters. A thorough study of both the control gate and the polarity gate behavior is conducted. The noise margin of the logic gates is measured and analyzed. The large noise margin enables the implementation of VT-drop circuits, a type of logic with reduced transistor number and simplified circuit design. Finally, the speed performance of the VT-drop and other circuits built by dual-gate devices is qualitatively analyzed. This work makes advancements in the field of ambipolar dual-gate TMD transistors, showing their potential for low-power, high-speed, and more flexible logic circuits. 
    more » « less
  3. ; (, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI))
    The tremendous growth in the number of Internet of Things (IoT) devices has increased focus on the energy efficiency and security of an IoT device. In this paper, we will present a design level, non-volatile adiabatic architecture for low-energy and Correlation Power Analysis (CPA) resistant IoT devices. IoT devices constructed with CMOS integrated circuits suffer from high dynamic energy and leakage power. To solve this, we look at both adiabatic logic and STT-MTJs (Spin Transfer Torque Magnetic Tunnel Junctions) to reduce both dynamic energy and leakage power. Furthermore, CMOS integrated circuits suffer from side-channel leakage making them insecure against power analysis attacks. We again look to adiabatic logic to design secure circuits with uniform power consumption, thus, defending against power analysis attacks. We have developed a hybrid adiabatic-MTJ architecture using two-phase adiabatic logic. We show that hybrid adiabatic-MTJ circuits are both low energy and secure when compared with CMOS circuits. As a case study, we have constructed one round of PRESENT and have shown energy savings of 64.29% at a frequency of 25 MHz. Furthermore, we have performed a correlation power analysis attack on our proposed design and determined that the key was kept hidden. 
    more » « less
  4. ; ; (, IEEE Transactions on Magnetics)
    Spin transfer torque magnetic random access memory (STT-MRAM) offers a promising solution for low-power and high-density memory due to its compatibility with CMOS, higher density, scalable nature, and non-volatility. However, the higher energy required to write bit cells has remained a key challenge for its adaptation into battery-operated smart handheld devices. The existing low-energy writing solutions require additional complex control logic mechanisms, further constraining the available area. In this research, we propose a solution to design energy-efficient write circuits by incorporating two techniques together. First, we propose the sinusoidal power clocking mechanism replacing the DC power supply in the conventional CMOS design. Second, we propose three lookup table (LUT)-based control logic circuits and one write circuit to reduce the area and further minimize energy dissipation. The experimental results are verified over the case study implementations of 4×4 STT-MRAM macro designed using bit cell configurations: i) one transistor and one magnetic tunnel junction (MTJ) (1T-1MTJ) and ii) four transistors and two MTJs (4T-2MTJ). The post-layout simulation for the frequency range from 250 kHz to 6.25 MHz shows that the write circuit, which uses the proposed LUT-based control logic circuits and a write driver with a sinusoidal power supply, achieves more than a 65.05% average energy saving compared to the CMOS counterpart. Furthermore, the write circuit, which uses the proposed 6T write driver with the sinusoidal power supply, shows an improvement in energy saving by more than 70.60% compared to the CMOS counterpart. We also verified that the energy-saving performance remains relatively consistent with the change in temperature and the tunneling magnetoresistance (TMR) ratio. 
    more » « less
  5. ; ; ; (, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems)
    In this paper, we propose an energy-efficient reconfigurable platform for in-memory processing based on novel 4-terminal spin Hall effect-driven domain wall motion devices that could be employed as both non-volatile memory cell and in-memory logic unit. The proposed designs lead to unity of memory and logic. The device to system level simulation results show that, with 28% area increase in memory structure, the proposed in-memory processing platform achieves a write energy ~15.6 fJ/bit with 79% reduction compared to that of SOT-MRAM counterpart while keeping the identical 1ns writing speed. In addition, the proposed in-memory logic scheme improves the operating energy by 61.3%, as compared with the recent non-volatile in-memory logic designs. An extensive reliability analysis is also performed over the proposed circuits. We employ Advanced Encryption Standard (AES) algorithm as a case study to elucidate the efficiency of the proposed platform at application level. Simulation results exhibit that the proposed platform can show up to 75.7% and 30.4% lower energy consumption compared to CMOS-ASIC and recent pipelined domain wall (DW) AES implementations, respectively. In addition, the AES Energy-Delay Product (EDP) can show 15.1% and 6.1% improvements compared to the DW-AES and CMOS-ASIC implementations, respectively. 
    more » « less
  • Citation Formats
  • MLA
  • APA
  • Chicago
  • BibTeX
  • Save / Share this Record
  • Send to Email