In this paper, we propose PIMA-Logic, as a novel Processing-in-Memory Architecture for highly flexible and efficient Logic computation. Insteadof integrating complex logic units in cost-sensitive memory, PIMA-Logic exploits a hardware-friendly approach to implement Boolean logic functions between operands either located in the same row or the same column within entire memory arrays. Furthermore, it can efficiently process more complex logic functions between multiple operands to further reduce the latency and power-hungry data movement. The proposed architecture is developed based on Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array and it can simultaneously work as a non-volatile memory and a reconfigurable in-memory logic. The device-to-architecture co-simulation results show that PIMA-Logic can achieve up to 56% and 31.6% improvements with respect to overall energy and delay on combinational logic benchmarks compared to recent Pinatubo architecture. We further implement an in-memory data encryption engine based on PIMA-Logic as a case study. With AES application, it shows 77.2% and 21% lower energy consumption compared to CMOS-ASIC and recent RIMPA implementation, respectively.
Compact Modeling and Design of Magneto-Electric Transistor Devices and Circuits
A Verilog-A based model for the magneto-electric field effect transistor (MEFET) device is implemented and a variety of logic functions based on this device are proposed. These models are used to capture energy consumption and delay per switching event and to benchmark the MEFET with respect to CMOS. Single-source MEFET devices can be used for conventional logic gates like NAND, NOR, inverter and buffer and more complex circuits like the full adder. The dual source MEFET is an enhanced version of the MEFET device which functions like a spin multiplexer (spin-MUXer). Circuits using MEFETs require fewer components than CMOS to generate the same logic operation. These devices display a high on-off ratio., unlike many magneto-electric devices., and they operate at very low voltages., resulting in lower switching energy. Benchmarking results show that these devices perform better in terms of energy and delay., for implementing more complex functions., than the basic logic gates.
- Award ID(s):
- 1740136
- Publication Date:
- NSF-PAR ID:
- 10096464
- Journal Name:
- 2018 31st IEEE International System-on-Chip Conference (SOCC)
- Page Range or eLocation-ID:
- 146 to 151
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Publisher's Version of Record
- https://doi.org/10.1109/SOCC.2018.8618494
