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1. Direct Fabrication of VIA Interconnects by Electrohydrodynamic Printing for Multi‐Layer 3D Flexible and Stretchable Electronics

   https://doi.org/10.1002/admt.202100280  

   Ren, Ping; Dong, Jingyan (June 2021, Advanced Materials Technologies)

   Abstract Multi‐layer electrical interconnects are critical for the development of integrated soft wearable electronic systems, in which functional devices from different layers need to be connected together by vertical interconnects. In this work, electrohydrodynamic (EHD) printing technology is studied to achieve multi‐layer flexible and stretchable electronics by direct printing vertical interconnects as vertical interconnect accesses (VIAs) using a low‐melting‐point metal alloy. The EHD printed metallic vertical interconnection represents a promising way for the direct fabrication of multilayer integrated electronics with metallic conductivity and excellent flexibility and stretchability. By controlling the printing conditions, vertical interconnects that can bridge different heights can be fabricated. To achieve reliable VIA connections under bending and stretching conditions, an epoxy protective structure is printed around the VIA interconnects to form a core‐shell structure. A stable electrical response is achieved under hundreds of bending cycles and during stretching/releasing cycles in a large range of tensile strain (0–40%) for the printed conductors with VIA interconnects. A few multi‐layer devices, including a multiple layer heater, and a pressure‐based touch panel are fabricated to demonstrate the capability of the EHD printing for the direct fabrication of vertical metallic VIA interconnects for flexible and stretchable devices. 

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2. Mitigation of Electromigration in Metal Interconnects via Hexagonal Boron Nitride as an Ångström‐Thin Passivation Layer

   https://doi.org/10.1002/aelm.202100002  

   Jeong, Yunjo; Douglas, Ossie; Misra, Utkarsh; Tanjil, Md Rubayat‐E; Watanabe, Kenji; Taniguchi, Takashi; Wang, Michael Cai (April 2021, Advanced Electronic Materials)

   Abstract Electromigration in metal interconnects remains a significant challenge in the continued scaling of integrated circuits towards ever‐smaller single‐nanometer nodes. Conventional damascene architectures of barrier/liner layers and conducting metal cause inevitable compromises between device performance and feature dimensions. In contrast to contemporary barrier/liner materials (e.g., Co, Ta, and Ru), an ultrathin passivation layer that can effectively mitigate electromigration is needed. At the ultimate atomically‐thin limit, 2D materials are promising candidates given their exceptional mechanical properties and impermeability. Here, a facile and effective approach is presented to mitigating electromigration in copper (Cu) interconnects via passivation with insulating monolayer 2D hexagonal boron nitride (hBN). The hBN‐passivated Cu interconnects, compared to otherwise identical but bare Cu interconnects, exhibit on average a >20% higher breakdown current density and a >2600% longer lifetime (at a high current density of 5.4 × 10⁷A cm⁻²). Post‐mortem metrology elucidates uniform conformal contact between the hBN‐passivated Cu interface and common failure features due to electromigration. 

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3. Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic Interconnects

   https://doi.org/10.1109/DAC18074.2021.9586311  

   Li, Yuan; Louri, Ahmed; Karanth, Avinash (December 2021, 58th ACM/IEEE Design Automation Conference (DAC))

   Chiplet-based architectures have been proposed to scale computing systems for deep neural networks (DNNs). Prior work has shown that for the chiplet-based DNN accelerators, the electrical network connecting the chiplets poses a major challenge to system performance, energy consumption, and scalability. Some emerging interconnect technologies such as silicon photonics can potentially overcome the challenges facing electrical interconnects as photonic interconnects provide high bandwidth density, superior energy efficiency, and ease of implementing broadcast and multicast operations that are prevalent in DNN inference. In this paper, we propose a chiplet-based architecture named SPRINT for DNN inference. SPRINT uses a global buffer to simplify the data transmission between storage and computation, and includes two novel designs: (1) a reconfigurable photonic network that can support diverse communications in DNN inference with minimal implementation cost, and (2) a customized dataflow that exploits the ease of broadcast and multicast feature of photonic interconnects to support highly parallel DNN computations. Simulation studies using ResNet50 DNN model show that SPRINT achieves 46% and 61% execution time and energy consumption reduction, respectively, as compared to other state-of-the-art chiplet-based architectures with electrical or photonic interconnects. 

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4. EM-GAN: Data-driven fast stress analysis for multi-segment interconnects

   Jin, W.; Sadiqbatcha, S.; Sun, Z.; Zhou, H.; Tan, S. X.-D. (October 2020, Proc. IEEE Int. Conf. on Computer Design (ICCD),)

   Electromigration (EM) analysis for complicated interconnects requires the solving of partial differential equations, which is expensive. In this paper, we propose a fast transient hydrostatic stress analysis for EM failure assessment for multi-segment interconnects using generative adversarial networks (GANs). Our work is inspired by the image synthesis and feature of generative deep neural networks. The stress evaluation of multi-segment interconnects, modeled by partial differential equations, can be viewed as time-varying 2D-images-to-image problem where the input is the multi-segment interconnects topology with current densities and the output is the EM stress distribution in those wire segments at the given aging time. We show that the conditional GAN can be exploited to attend the temporal dynamics for modeling the time-varying dynamic systems like stress evolution over time. The resulting algorithm, called {\it EM-GAN}, can quickly give accurate stress distribution of a general multi-segment wire tree for a given aging time, which is important for full-chip fast EM failure assessment. Our experimental results show that the EM-GAN shows 6.6\% averaged error compared to COMSOL simulation results with orders of magnitude speedup. It also delivers $$8.3 \times$$ speedup over state-of-the-art analytic based EM analysis solver. 

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5. Multi‐Objective Optimization for Rapid Identification of Novel Compound Metals for Interconnect Applications

   https://doi.org/10.1002/smll.202308784  

   Ramdas, Akash; Zhou, Guanyu; Li, Yansong; Lu, Ping‐Lien; Antoniuk, Evan R; Reed, Evan J; Hinkle, Christopher L; da_Jornada, Felipe H (April 2024, Small)

   Interconnect materials play the critical role of routing energy and information in integrated circuits. However, established bulk conductors, such as copper, perform poorly when scaled down beyond 10 nm, limiting the scalability of logic devices. Here, a multi‐objective search is developed, combined with first‐principles calculations, to rapidly screen over 15,000 materials and discover new interconnect candidates. This approach simultaneously optimizes the bulk electronic conductivity, surface scattering time, and chemical stability using physically motivated surrogate properties accessible from materials databases. Promising local interconnects are identified that have the potential to outperform ruthenium, the current state‐of‐the‐art post‐Cu material, and also semi‐global interconnects with potentially large skin depths at the GHz operation frequency. The approach is validated on one of the identified candidates, CoPt, using both ab initio and experimental transport studies, showcasing its potential to supplant Ru and Cu for future local interconnects. 

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