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1. Rapid Inverse Design of GaN-on-GaN Diode with Guard Ring Termination for BV and (V F Q) −1 Co-Optimization

   https://doi.org/10.1109/ISPSD57135.2023.10147511  

   Yee, Nathan ; Lu, Albert ; Wang, Yifan ; Porter, Matthew ; Zhang, Yuhao ; Wong, Hiu Yung ( May 2023 , 2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD))

   GaN-on-GaN vertical diode is a promising device for next-generation power electronics. Its breakdown voltage (BV) is limited by edge termination designs such as guard rings. The design space of guard rings is huge and it is difficult to optimize manually. In this paper, we propose an effective inverse design strategy to co-optimize BV and (V F Q) −1 , where BV, V F , and Q are the breakdown voltage, forward voltage, and reserve capacitive charge of the diode, respectively. Using rapid Technology Computer-Aided-Design (TCAD) simulations, neural network (NN), and Pareto front generation, a GaN-on-GaN diode is optimized within 24 hours. We can obtain structures with 200V higher BV at medium (V F Q) −1 or find a nearly ideal BV structure with 25% higher BV 2 /R on compared to the best randomly generated TCAD data. 

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2. Schottky contacts to N-polar GaN with SiN interlayer for elevated temperature operation

   https://doi.org/10.1063/5.0083588  

   Khachariya, Dolar ; Szymanski, Dennis ; Reddy, Pramod ; Kohn, Erhard ; Sitar, Zlatko ; Collazo, Ramón ; Pavlidis, Spyridon ( April 2022 , Applied Physics Letters)

   In this Letter, we unveil the high-temperature limits of N-polar GaN Schottky contacts enhanced by a low-pressure chemical vapor deposited (LPCVD) SiN interlayer. Compared to conventional Schottky diodes, the insertion of a 5 nm SiN lossy dielectric interlayer in-between Ni and N-polar GaN increases the turn-on voltage ( V ON ) from 0.4 to 0.9 V and the barrier height ( ϕ B ) from 0.4 to 0.8 eV. This modification also reduces the leakage current at zero bias significantly: at room temperature, the leakage current in the conventional Schottky diode is >10 3 larger than that observed in the device with the SiN interlayer, while at 200 °C, this ratio increases to 10 5 . Thus, the rectification ratio (I ON /I OFF ) at ±1.5 V reduces to less than one at 250 °C for the conventional Schottky diode, whereas for SiN-coated diodes, rectification continues until 500 °C. The I–V characteristics of the diode with an SiN interlayer can be recovered after exposure to 400 °C or lower. Contact degradation occurs at 500 °C, although devices are not destroyed yet. Here, we report N-polar GaN Schottky contact operation up to 500 °C using an LPCVD SiN interlayer. 

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3. Distributed polarization-doped GaN p–n diodes with near-unity ideality factor and avalanche breakdown voltage of 1.25 kV

   https://doi.org/10.1063/5.0083302  

   Nomoto, Kazuki ; Li, Wenshen ; Song, Bo ; Hu, Zongyang ; Zhu, Mingda ; Qi, Meng ; Protasenko, Vladimir ; Zhang, Zexuan ; Pan, Ming ; Gao, Xiang ; et al ( March 2022 , Applied Physics Letters)

   Polarization-induced (Pi) distributed or bulk doping in GaN, with a zero dopant ionization energy, can reduce temperature or frequency dispersions in impurity-doped p–n junctions caused by the deep-acceptor-nature of Mg, thus offering GaN power devices promising prospects. Before comprehensively assessing the benefits of Pi-doping, ideal junction behaviors and high-voltage capabilities should be confirmed. In this work, we demonstrate near-ideal forward and reverse I–V characteristics in Pi-doped GaN power p–n diodes, which incorporates linearly graded, coherently strained AlGaN layers. Hall measurements show a net increase in the hole concentration of 8.9 × 10¹⁶ cm⁻³in the p-layer as a result of the polarization charge. In the Pi-doped n-layer, a record-low electron concentration of 2.5 × 10¹⁶ cm⁻³is realized due to the gradual grading of Al_0-0.72GaN over 1  μm. The Pi-doped p–n diodes have an ideality factor as low as 1.1 and a 0.10 V higher turn-on voltage than the impurity-doped p–n diodes due to the increase in the bandgap at the junction edge. A differential specific on-resistance of 0.1 mΩ cm²is extracted from the Pi-doped p–n diodes, similar with the impurity-doped counterpart. The Pi-doped diodes show an avalanche breakdown voltage of ∼1.25 kV, indicating a high reverse blocking capability even without an ideal edge-termination. This work confirms that distributed Pi-doping can be incorporated in high-voltage GaN power devices to increase hole concentrations while maintaining excellent junction properties.

    

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4. Silicon implantation and annealing in β -Ga2O3: Role of ambient, temperature, and time

   https://doi.org/10.1063/5.0184946  

   Gann, Katie R ; Pieczulewski, Naomi ; Gorsak, Cameron A ; Heinselman, Karen ; Asel, Thaddeus J ; Noesges, Brenton A ; Smith, Kathleen T ; Dryden, Daniel M ; Xing, Huili Grace ; Nair, Hari P ; et al ( January 2024 , Journal of Applied Physics)

   Optimizing thermal anneals of Si-implanted β-Ga2O3 is critical for low resistance contacts and selective area doping. We report the impact of annealing ambient, temperature, and time on the activation of room temperature ion-implanted Si in β-Ga2O3 at concentrations from 5 × 1018 to 1 × 1020 cm−3, demonstrating full activation (>80% activation, mobilities >70 cm2/V s) with contact resistances below 0.29 Ω mm. Homoepitaxial β-Ga2O3 films, grown by plasma-assisted molecular beam epitaxy on Fe-doped (010) substrates, were implanted at multiple energies to yield 100 nm box profiles of 5 × 1018, 5 × 1019, and 1 × 1020 cm−3. Anneals were performed in an ultra-high vacuum-compatible quartz furnace at 1 bar with well-controlled gas compositions. To maintain β-Ga2O3 stability, pO2 must be greater than 10−9 bar. Anneals up to pO2 = 1 bar achieve full activation at 5 × 1018 cm−3, while 5 × 1019 cm−3 must be annealed with pO2 ≤ 10−4 bar, and 1 × 1020 cm−3 requires pO2 < 10−6 bar. Water vapor prevents activation and must be maintained below 10−8 bar. Activation is achieved for anneal temperatures as low as 850 °C with mobility increasing with anneal temperatures up to 1050 °C, though Si diffusion has been reported above 950 °C. At 950 °C, activation is maximized between 5 and 20 min with longer times resulting in decreased carrier activation (over-annealing). This over-annealing is significant for concentrations above 5 × 1019 cm−3 and occurs rapidly at 1 × 1020 cm−3. Rutherford backscattering spectrometry (channeling) suggests that damage recovery is seeded from remnant aligned β-Ga2O3 that remains after implantation; this conclusion is also supported by scanning transmission electron microscopy showing retention of the β-phase with inclusions that resemble the γ-phase.

    

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5. Integrable Quasivertical GaN U‐Shaped Trench‐Gate Metal‐Oxide‐Semiconductor Field‐Effect Transistors for Power and Optoelectronic Integrated Circuits

   https://doi.org/10.1002/pssa.201900615  

   Guo, Zhibo ; Hitchcock, Collin ; Karlicek, Jr., Robert F. ; Piao, Guanxi ; Yano, Yoshiki ; Koseki, Shuuichi ; Tabuchi, Toshiya ; Matsumoto, Koh ; Bulsara, Mayank ; Chow, T. Paul ( November 2019 , physica status solidi (a))

   Integrable, hexagonal‐cell, high‐voltage, quasivertical GaN power U‐shaped trench‐gate metal‐oxide‐semiconductor field‐effect transistors (UMOSFETs) fabricated in the n+/p/n−/n+ GaN epilayers on sapphire substrates are experimentally demonstrated for the first time. Hexagonal cells, with pitch ranging from 11 to 20 μm, are used to obtain identicalm‐plane sidewalls for gate and drain trenches. Metallization compatible with light‐emitting diode (LED) optoelectronic integration is used. The dependence of device performance on different parameters is systematically studied and analyzed. The lowestR_on,spof 23 mΩ cm²and highest drain saturation current of 295 A cm⁻²are obtained by measuring an 11 μm cell‐pitch UMOSFET. The breakdown voltage of an open‐cell design variation (208 V) is higher than that of a closed‐cell design variation (89 V), whereas the closed‐cell design exhibits a lower off‐state leakage current of 1.4 × 10⁻⁵A cm⁻². A hexagonal‐cell specific on‐state resistanceR_cell,spof 8.5 mΩ cm²and buried n+ layer sheet resistanceR_BL,□of 223 Ω □⁻¹are extracted by applying a 2D resistance network model to UMOSFETs of varying sizes.

    

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