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1. A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures

   https://doi.org/10.1109/DAC18072.2020.9218654  

   Zheng, Hao; Wang, Ke; Louri, Ahmed (July 2020, 57th ACM/IEEE Design Automation Conference (DAC))

   null (Ed.)

   Heterogeneous manycore architectures are deployed to simultaneously run multiple and diverse applications. This requires various computing capabilities (CPUs, GPUs, and accelerators), and an efficient network-on-chip (NoC) architecture to concurrently handle diverse application communication behavior. However, supporting the concurrent communication requirements of diverse applications is challenging due to the dynamic application mapping, the complexity of handling distinct communication patterns and limited on-chip resources. In this paper, we propose Adapt-NoC, a versatile and flexible NoC architecture for chiplet-based manycore architectures, consisting of adaptable routers and links. Adapt-NoC can dynamically allocate disjoint regions of the NoC, called subNoCs, for concurrently-running applications, each of which can be optimized for different communication behavior. The adaptable routers and links are capable of providing various subNoC topologies, satisfying different latency and bandwidth requirements of various traffic patterns (e.g. all-to-all, one-to-many). Full system simulation shows that AdaptNoC can achieve 31% latency reduction, 24% energy saving and 10% execution time reduction on average, when compared to prior designs. 

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2. Reconfigurable Network-on-Chip Security Architecture

   https://doi.org/10.1145/3406661  

   Charles, Subodha; Mishra, Prabhat (October 2020, ACM Transactions on Design Automation of Electronic Systems)

   null (Ed.)

   Growth of the Internet-of-things has led to complex system-on-chips (SoCs) being used in the edge devices in IoT applications. The increased complexity is demanding designers to consider several critical factors, such as dynamic requirement changes, long application life, mass production, and tight time-to-market deadlines. These requirements lead to more complex security concerns. SoC manufacturers outsource some of the intellectual property cores integrated on the SoC to untrusted third-party vendors. The untrusted intellectual properties can contain malicious implants, which can launch attacks using the resources provided by the on-chip interconnection network, commonly known as the network-on-chip (NoC). Existing efforts on securing NoC have considered lightweight encryption, authentication, and other attack detection mechanisms such as denial-of-service and buffer overflows. Unfortunately, these approaches focus on designing statically optimized security solutions. As a result, they are not suitable for many IoT systems with long application life and dynamic requirement changes. There is a critical need to design reconfigurable security architectures that can be dynamically tuned based on changing requirements. In this article, we propose a tier-based reconfigurable security architecture that can adapt to different use-case scenarios. We explore how to design an efficient reconfigurable architecture that can support three popular NoC security mechanisms (encryption, authentication, and denial-of-service attack detection and localization) and implement suitable dynamic reconfiguration techniques. We evaluate our proposed framework by running standard benchmarks enabling different tiers of security and provide a comprehensive analysis of how different levels of security can affect application performance, energy efficiency, and area overhead. 

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3. Lightweight Anonymous Routing in NoC based SoCs

   https://doi.org/10.23919/DATE48585.2020.9116572  

   Charles, Subodha; Logan, Megan; Mishra, Prabhat (March 2020, Design Automation & Test in Europe (DATE))

   System-on-Chip (SoC) supply chain is widely acknowledged as a major source of security vulnerabilities. Potentially malicious third-party IPs integrated on the same Network-on-Chip (NoC) with the trusted components can lead to security and trust concerns. While secure communication is a well studied problem in computer networks domain, it is not feasible to implement those solutions on resource-constrained SoCs. In this paper, we present a lightweight anonymous routing protocol for communication between IP cores in NoC based SoCs. Our method eliminates the major overhead associated with traditional anonymous routing protocols while ensuring that the desired security goals are met. Experimental results demonstrate that existing security solutions on NoC can introduce significant (1.5X) performance degradation, whereas our approach provides the same security features with minor (4%) impact on performance. 

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4. Viscoelastic Influence On the Board Level Assessment of Wafer Level Packages Under Drop Impact and Under Thermal Cycling

   https://doi.org/10.1115/1.4054784  

   Misrak, Abel; Bhandari, Rabin; Agonafer, Dereje (June 2022, Journal of Electronic Packaging)

   Abstract Structural components such as printed circuit boards (PCBs) are critical in the thermomechanical reliability assessment of electronic packages. Previous studies have shown that geometric parameters such as thickness and mechanical properties like elastic modulus of PCBs have direct influence on the reliability of electronic packages. Elastic material properties of PCBs are commonly characterized using equipment such as tensile testers and used in computational studies. However, in certain applications viscoelastic material properties are important. Viscoelastic influence on materials is evident when one exceeds the glass transition temperature of materials. Operating conditions or manufacturing conditions such as lamination and soldering may expose components to temperatures that exceed the glass transition temperatures. Knowing the viscoelastic behavior of the different components of electronic packages is important in order to perform accurate reliability assessment and design components such as printed circuit boards (PCBs) that will remain dimensionally stable after the manufacturing process. Previous researchers have used creep and stress relaxation test data to obtain the Prony series terms that represent the viscoelastic behavior and perform analysis. Others have used dynamic mechanical analysis in order to obtain frequency domain master curves that were converted to time domain before obtaining the Prony series terms. In this paper, nonlinear solvers were used on frequency domain master curve results from dynamic mechanical analysis to obtain Prony series terms and perform finite element analysis on the impact of adding viscoelastic properties when performing reliability assessment. The computational study results were used to perform comparative assessment to understand the impact of including viscoelastic behavior in reliability analysis under thermal cycling and drop testing for Wafer Level Chip Scale Packages. 

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5. Accelerating Graph Computations on 3D NoC-enabled PIM Architectures

   https://doi.org/10.1145/3564290  

   Choudhury, Dwaipayan; Xiang, Lizhi; Rajam, Aravind Sukumaran; Kalyanaraman, Ananth; Pande, Partha Pratim (October 2022, ACM Transactions on Design Automation of Electronic Systems)

   Graph application workloads are dominated by random memory accesses with poor locality. To tackle the irregular and sparse nature of computation, ReRAM-based Processing-in-Memory (PIM) architectures have been proposed recently. Most of these ReRAM architecture designs have focused on mapping graph computations into a set of multiply-and-accumulate (MAC) operations. ReRAMs also offer a key advantage in reducing memory latency between cores and memory by allowing for processing-in-memory (PIM). However, when implemented on a ReRAM-based manycore architecture, graph applications still pose two key challenges – significant storage requirements (particularly due to wasted zero cell storage), and significant amount of on-chip traffic. To tackle these two challenges, in this paper we propose the design of a 3D NoC-enabled ReRAM-based manycore architecture. Our proposed architecture incorporates a novel crossbar-aware node reordering to reduce ReRAM storage requirements. Secondly, its 3D NoC-enabled design reduces on-chip communication latency. Our architecture outperforms the state-of-the-art in ReRAM-based graph acceleration by up to 5x in performance while consuming up to 10.3x less energy for a range of graph inputs and workloads. 

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