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1. A Low Phase Noise 28 GHz VCO Using Transformer-based Q-enhanced Active Impedance Converter

   https://doi.org/10.1109/IMS37962.2022.9865389  

   Hoque, Md Aminul; Chahadori, Mohammad; Mokri, Mohammad Ali; Mohapatra; Soumen Mohapatra; Kar, Dipan; Heo, Deukhyoun (July 2022, IEEE International Microwave Symposium)

   This paper presents a low phase noise 28 GHz voltage-controlled oscillator (VCO) using a transformer-based active impedance converter to enhance the quality factor (Q) of the capacitor in the resonator. The active impedance converter can enhance the Q of a capacitor bank and varactor by 25-40% across the VCO’s tuning range. The proposed VCO is fabricated using the proposed transformer-based Q-enhancement impedance converter in a standard 65 nm CMOS process. The VCO achieves a 15.9% measured fractional frequency tuning range and phase noise of −107.6 dBc/Hz at 1 MHz offset from 28 GHz oscillation frequency while occupying only 0.05 mm2 area (200 μm × 250 μm). The VCO consumes 5.1 mW power, resulting in an excellent figure-of-merit (FoM) of 189.4 dBc/Hz and a figure-of-merit-with-area (FoMA) of 202.8 dBc/Hz. 

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2. Zero-Power Feed-Forward Spur Cancelation for Supply-Regulated CMOS Ring PLLs

   Agarwal, P.; Kim, J. H.; Pande, P. P.; Heo, D. (January 2018, IEEE transactions on very large scale integration (VLSI) systems)

   A new reference-spur cancelation technique is presented for supply-regulated ring-oscillator-based integer-N phaselocked loops (PLLs). A passive RC filter is used to implement a feed-forward (FF) spur-coupling path to perform spur cancelation at the PLL control signal. The proposed technique achieves a simulated spur cancelation of about 22 dB at the first spur harmonic. The simulated postcancelation spur value is -79 dBc for an oscillator gain of 0.1 GHz/V and -46 dBc for an oscillator gain of 6 GHz/V. Spur cancelation is also robust against large process, voltage, and temperature variations in the gain and bandwidth of the FF path. A 1-GHz integerN PLL prototype in a 65-nm CMOS process has a measured cancelation of 19.5 and 13 dB at the first and the second spur harmonic, respectively, with 320 μW of total power consumption. The PLL prototype has an oscillator gain of 1.5 GHz/V, which results in a postcancelation spur of -53 dBc. The proposed zero-power technique is suitable for low-power PLLs as it achieves a large spur cancelation without requiring any additional power consumption or calibration. 

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3. A 2.4 GHz low-power and compact 3-bit active phase shifter utilizing miller capacitance

   https://doi.org/10.1016/j.mejo.2023.105914  

   Qi, Yu; Kines, Michael; Ellicott, Samuel; Khalil, Waleed; Lavasani, Hossein Miri (October 2023, Microelectronics Journal)

   A low-power and compact 3-bit active phase shifter is designed and implemented in a 22 nm FDSOI CMOS process. A modified inverter-based topology, which takes advantage of miller capacitance, is used to create a compact and low-power solution, resulting in 10 and 90 x reduction in the power and chip area, respectively, for a given phase shift, compared to the standard inverter-based topology. At the same time, the proposed phase shifter exhibits less sensitivity to device mismatch. The proposed design measures 0.004 mm2, consumes 1.8 mW, and delivers up to 65°of phase shift with RMS phase and amplitude error of 3.85°and ±0.34 dB, respectively. The measured die-to-die variation is also confined to ±6.2°, which is 10% of the full range 

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4. A 49-63 GHz Phase-locked FMCW Radar Transceiver for High Resolution Applications

   Liu, Xuyang; Maktoomi, Md Hedayatullah; Alesheikh, Mahdi; Heydari, Payam; Aghasi, Hamidreza (October 2023, IEEE European Solid State Circuits Conference)

   TPC of IEEE ESSCIRC Conference (Ed.)

   This paper presents an mmWave FMCW radar that can achieve sub-centimeter-scale range resolution at 14- GHz chirp-bandwidth while maintaining the radar range beyond 50 meters. To meet the requirements on power efficiency, chirp linearity, and signal-to-noise ratio (SNR), a phase-locked steppedchirp FMCW radar architecture is introduced. Specifically, a fully integrated radar transceiver comprising an interleaved frequency-segmented phase-locked transmitter and a segmented receiver architecture with high sensitivity is presented. The proposed design addresses the limitations of conventional typeII phase-locked loops (PLLs) in extending the radar bandwidth across multiple sub-bands with identical chirp profiles. Fabricated in a 22nm FD-SOI technology, the prototype chip comprises two sub-bands with 14 GHz of free-running bandwidth and 10 GHz of phase-locked bandwidth. The system achieves -101.7 dBc/Hz phase noise at 1 MHz offset, 8 dBm of effective isotropic radiated power (EIRP), 10 dB noise figure (NF), and 362.6 mW collective power consumption of transmitter and receiver arrays. 

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5. A 60-GHz Digital Sub-Sampling Integer-N Phase-Locked Loop

   https://doi.org/10.1109/WMCS49442.2020.9172416  

   Rong, Chao; Mondal, Susnata; Carley, L. Richard; Paramesh, Jeyanandh (May 2020, 2020 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS))

   null (Ed.)

   Digital phase-locked loops (DPLL) are finding new applications in highly demanding contexts such as frequency synthesis for millimeter-wave (mm-wave) communications and clock generation for ultra-high-speed wireline transceivers. In a typical DPLL, however, a time-to-digital converter (TDC) with fine time resolution, high linearity and high dynamic range is required to meet stringent noise and spur performance requirements, which negatively impacts the power consumption in a DPLL. A bang-bang phase-detector (BBPD) outperforms a multi-bit TDC in terms of its’ jitter-power tradeoff, but its’ highly non-linear phase detection characteristic limits the locking speed of the loop. This research explores the design and of a 60 GHz digital sub-sampling phase-locked loop that uses a BBPD loop for frequency tracking and a coarse TDC loop for fast frequency acquisition. A prototype of the DPLL is designed in a 28-nm CMOS technology with supporting evidence through extensive simulations. 

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