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A convenient method based on deep neural networks and an evolutionary algorithm is proposed for the inverse design of FinFET SRAM cells. Inverse design helps designers who have less device physics knowledge obtain cell configurations that provide the desired performance metrics under selected wearout conditions, such as a set specific stress time and use scenario that creates a specific activity level (duty cycle and transition rate). The cell configurations being considered consists of various process parameters, such as gate length and fin height, in the presence of variations due to process and wearout. The front-end mechanisms related to wearout include negative bias temperature instability (NBTI), hot carrier injection (HCI), and random telegraph noise (RTN). The process of inverse design is achieved quickly and at good accuracy. 

Advanced FinFET SRAMs undergo reliability degradation due to various front-end and back-end wearout mechanisms. The design of reliable SRAMs benefits from accurate wearout models that are calibrated by accelerated test. With respect to testing, the accelerated conditions which can help separate the dominant wearout mechanisms related to circuit failure is crucial for model calibration and reliability prediction. In this paper, the estimation of optimal accelerated test regions for a 14nm FinFET SRAM under various wearout mechanisms is presented. The dominant regions for specific mechanisms are compared and analyzed for effective testing. It is observed that for our SRAM example circuit only bias temperature instability (BTI) and middle-of-line time-dependent dielectric breakdown (MTDDB) have test regions where their failures can be isolated, while the other mechanisms can’t be extracted individually due to acceptable regions’ overlap. Meanwhile, the SRAM cell activity distribution has a small influence on test regions and selectivity. 

This paper proposes a methodology to find optimal accelerated test regions for lifetime parameter estimation for not only the traditional reliability concern, frontend-of-line dielectric breakdown (FEOL TDDB), but also the newly emerging wearout mechanism, middle-of-line time dependent dielectric breakdown (MOL TDDB) in 14nm FinFET technology. The framework to find the optimal test regions is introduced; the error estimating methodology is discussed in detail. Three digital circuits are presented for evaluation and comparison. The optimal test regions depend on the circuit size as well as the types of standard cells in the circuits. To ensure accurate lifetime parameter estimation, both error from sampling and error from selectivity should be considered at the same time. As a general guideline, higher estimation accuracy will be achieved by testing gate TDDB lifetime parameters at higher voltages, while testing middle-of-line TDDB at higher temperatures. 

This paper presents a lifetime simulator for both Front-End-of-Line (FEOL) time dependent dielectric breakdown (TDDB) and the newly emerging Middle-of-Line (MOL) time dependent dielectric breakdown for FinFET technology. A lifetime assessment flow for digital circuits and microprocessors is proposed for the target wearout mechanisms, and its associated vulnerable feature extraction algorithms are discussed in detail. Our simulator incorporates the detailed electrical stress, temperature, linewidth of each standard cell within the digital circuit and microprocessor. Also, FEOL TDDB and MOL TDDB lifetimes are combined in the calculation of TDDB lifetime. Circuit designers can use the resulting lifetime information to guide and improve their circuits to make them more robust and reliable way.