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Abstract Nanoscale transistors demand aggressive scaling of all channel dimensions—length, width and thickness. Two-dimensional semiconductors (2DS) provide the ultimate thickness limit, yet good device performance has largely remained restricted to micrometre-wide channels. Here we report monolayer 2DS nanoribbon transistors with both n- and p-type operation, fabricated by a top-down multipatterning process that includes ‘anchored’ contacts to limit nanoribbon delamination. This approach achieves channel lengths and widths down to 25–30 nm, with minimal edge degradation confirmed through nanoscale characterization, including tip-enhanced photoluminescence. Integrated with thin high-κgate dielectrics, the devices deliver on-state currents up to 560, 420 and 130 µA µm⁻¹at a drain-to-source voltage of 1 V for n-type MoS₂, n-type WS₂and p-type WSe₂, respectively. These results exceed prior single-gated 2DS nanoribbon reports, with WS₂improving by more than two orders of magnitude, even for normally off (enhancement-mode) operation. Overall, these findings position top-down patterned 2DS nanoribbons as promising building blocks for future nanosheet transistor architectures. 

Abstract The ability to control phase structures and surface sites of ultrasmall alloy nanoparticles under reaction conditions is essential for preparing catalysts by design. This is, however, challenging due to limited understanding of the atomic‐scale phases and their correlation with the ensemble‐averaged structures and activities of catalysts during catalytic reactions. We reveal here a dynamic structural stability of alumina‐supported ultrasmall and equiatomic copper‐gold alloy nanoparticles under reaction conditions as a model system in the in situ/operando study. In situ atomic‐scale morphological tracking under oxygen reveals temperature‐dependent dynamic crystalline‐amorphous dual‐phase structures, showing dynamic stability over an elevated temperature range. This atomic‐scale dynamic phase stability coincides with a “conversion plateau” observed for carbon monoxide oxidation on the catalyst. It is substantiated by the stable lattice ordering/disordering structures and surface sites with oscillatory characteristics shown by operando ensemble‐average structural tracking of the catalyst during the oxidation reaction. The understanding of the atomic‐scale dynamic phase structures in correlation with the ensemble‐average dynamic ordering/disordering phase structures and surface sites provides fresh insights into the unique synergy of the supported alloy nanoparticles. This understanding has implications for the design and structural tuning of active and stable ultrasmall alloy catalysts under elevated temperatures. 

With the prosperous development of Deep Neural Network (DNNs), numerous Process-In-Memory (PIM) designs have emerged to accelerate DNN models with exceptional throughput and energy-efficiency. PIM accelerators based on Non-Volatile Memory (NVM) or volatile memory offer distinct advantages for computational efficiency and performance. NVM based PIM accelerators, demonstrated success in DNN inference, face limitations in on-device learning due to high write energy, latency, and instability. Conversely, fast volatile memories, like SRAM, offer rapid read/write operations for DNN training, but suffer from significant leakage currents and large memory footprints. In this paper, for the first time, we present a fully-digital sparse processing in hybrid NVM-SRAM design, synergistically combines the strengths of NVM and SRAM, tailored for on-device continual learning. Our designed NVM and SRAM based PIM circuit macros could support both storage and processing of N:M structured sparsity pattern, significantly improving the storage and computing efficiency. Exhaustive experiments demonstrate that our hybrid system effectively reduces area and power consumption while maintaining high accuracy, offering a scalable and versatile solution for on-device continual learning.