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A widely-regarded approach in Printed Circuit Board (PCB) reverse engineering (RE) uses non-destructive Xray computed tomography (CT) to produce three-dimensional volumes with several slices of data corresponding to multi-layered PCBs. The noise sources specific to X-ray CT and variability from designers make it difficult to acquire the features needed for the RE process. Hence, these X-ray CT images require specialized image processing techniques to examine the various features of a single PCB to later be translated to a readable CAD format. Previously, we presented an approach where the Hough Circle Transform was used for initial feature detection, and then an iterative false positive removal process was developed specifically for detecting vias on PCBs. Its performance was compared to an off-the-shelf application of the Mask Region-based Convolutional Network (M-RCNN). M-RCNN is an excellent deep learning approach that is able to localize and classify numerous objects of different scales within a single image. In this paper, we present a version of M-RCNN that is fine-tuned for via detection. Changes include polygon boundary annotations on the single X-ray images of vias for training and transfer learning to leverage the full potential of the network. We discuss the challenges of detecting vias using deep learning, our working solution, and our experimental procedure. Additionally, we provide a qualitative evaluation of our approach and use quantitative metrics to compare the proposed approach with the previous iterative one. 

Today’s globalized supply chain for electronics design, fabrication, and distribution has resulted in a proliferation of counterfeit chips. Recycled and remarked chips are the most common counterfeit types in the market, and prior work has shown that physical inspection is the best approach to detect them. However, it can be time-consuming, expensive, and destructive while relying on the use of subject matter experts. This paper proposes a low-cost, automated detection technique that examines surface variations within and between chips to identify defective chips. Further, it can estimate the location of the defects for additional analysis. The proposed method only requires a cheap IR camera-based setup to capture images of the chip package surface and is completely unsupervised and non-destructive. Experimental results on 25 chips in our lab demonstrate 100% detection accuracy. 

Modern integrated circuits (ICs) possess several countermeasures to safeguard sensitive data and information stored in the device. In recent years, semi-invasive physical attacks based on optical debugging techniques have proven to be capable of easily bypassing these security measures implemented in the chip. Optical attacks can reveal the data stored in memory, cache and register through various methods such as photon emission analysis, laser fault injection, laser voltage probing, and thermal laser stimulation. The above-mentioned methods, which employ laser scanning microscopy and photon emission microscopy, are effective because the silicon substrate is transparent to near-infrared (NIR) photons. Therefore, the most vulnerable part of an IC to optical attacks is the backside, where the chip's transistors can be accessed and probed with a NIR laser beam. Although different optical attack detection and … 

Scanning Electron Microscopy (SEM) is a common imaging modality used in the semiconductor industry particularly for failure analysis [1, 2]. In addition, with the recent growing concern of physical attacks on electronics with malicious intent, SEMs are becoming more attractive for hardware assurance and especially, Reverse Engineering (RE)[4]. However, RE requires long hours of imaging for an IC even if it is done automatically. In [3], the estimated time to image an IC of size 1.5 mm x 1.5 mm employing a 130nm node technology with high resolution went up to 30 days. With the ongoing trend of adding more structures onto a limited space on the IC, the imaging time frame is becoming unfeasible. This drawback would be manageable in situations where there is a prior knowledge on the exact location to be imaged. However, in case of hardware assurance and reverse engineering, where all the structures in the …