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Topological insulators (TIs) have attracted significant attention in photonics and acoustics due to their unique physical properties and promising applications. Electronics has recently emerged as an exciting arena to study various topological phenomena because of its advantages in building complex topological structures. Here, we explore TIs on an integrated circuit (IC) platform with a standard complementary metal-oxide-semiconductor technology. Based on the Su–Schrieffer–Heeger model, we design a fully integrated topological circuit chain using multiple capacitively-coupled inductor–capacitor resonators. We perform comprehensive post-layout simulations on its physical layout to observe and evaluate the salient topological features. Our results demonstrate the existence of the topological edge state and the remarkable robustness of the edge state against various defects. Our work shows the feasibility and promise of studying TIs with IC technology, paving the way for future explorations of large-scale topological electronics on the scalable IC platform.

Harnessing parity–time symmetry with balanced gain and loss profiles has created a variety of opportunities in electronics from wireless energy transfer to telemetry sensing and topological defect engineering. However, existing implementations often employ ad hoc approaches at low operating frequencies and are unable to accommodate large-scale integration. Here we report a fully integrated realization of parity–time symmetry in a standard complementary metal–oxide–semiconductor process technology. Our work demonstrates salient parity–time symmetry features such as phase transition as well as the ability to manipulate broadband microwave generation and propagation beyond the limitations encountered by existing schemes. The system shows 2.1 times the bandwidth and 30% noise reduction compared to conventional microwave generation in the oscillatory mode, and displays large non-reciprocal microwave transport from 2.75 to 3.10 GHz in the non-oscillatory mode due to enhanced nonlinearities. This approach could enrich integrated circuit design methodology beyond well-established performance limits and enable the use of scalable integrated circuit technology to study topological effects in high-dimensional non-Hermitian systems.

The development of FPGA-based applications using HLS is fraught with performance pitfalls and large design space exploration times. These issues are exacerbated when the application is complicated and its performance is dependent on the input data set, as is often the case with graph neural network approaches to machine learning. Here, we introduce HLPerf, an open-source, simulation-based performance evaluation framework for dataflow architectures that both supports early exploration of the design space and shortens the performance evaluation cycle. We apply the methodology to GNNHLS, an HLS-based graph neural network benchmark containing 6 commonly used graph neural network models and 4 datasets with distinct topologies and scales. The results show that HLPerf achieves over 10 000 × average simulation acceleration relative to RTL simulation and over 400 × acceleration relative to state-of-the-art cycle-accurate tools at the cost of 7% mean error rate relative to actual FPGA implementation performance. This acceleration positions HLPerf as a viable component in the design cycle.