More Like this

1. Hybrid PUF for Counterfeit Mitigation

   Ebenezer, P.; Chen, D.; and Geiger, R.L. (January 2021, Proceedings GOMACTech)

   A subthreshold hybrid PUF-embedded authentication circuit is proposed to mitigate the financial incentives that drive the counterfeit community and to encourage the COTS manufacturers to use authentication for system identification in their parts. The proposed hybrid PUF with cross-coupled inverters and a delay-based PUF strategy has sufficient entropy for authentication and a reduced number of transistors per bit. The area efficient fingerprint circuit does not require additional die area, pins, or power overhead. The performance of the primary circuit is unaffected by the fingerprint circuit. The hybrid circuit designed in a 65 nm CMOS process is discussed. 

   more » « less
2. Authentication Circuit with Low Incorporation Barrier for COTs Manufacturers

   Ebenezer, P. (July 2019, Proceedings of the IEEE National Aerospace and Electronics Conference NAECON)

   A simple PUF-based authentication circuit is proposed that will lower the entry barrier for counterfeit countermeasures by COTs manufacturers of integrated circuits. The on-chip fingerprint circuit does not require additional die area, I/O pins, or a separate read-out circuit. This approach to assuring integrity in the semiconductor supply chain will result in negative financial incentives for counterfeiters. An 80 bit authentication circuit which includes a 16 bit frame header has been designed in a UMC 65nm process with an area estimate of 0.01 mm2. 

   more » « less
3. Authentication Circuit with Low Incorporation Barrier for COTs Manufacturers

   Ebenezer, P. (July 2019, Proceedings of the IEEE National Aerospace and Electronics Conference NAECON)

   A simple PUF-based authentication circuit is proposed that will lower the entry barrier for counterfeit countermeasures by COTs manufacturers of integrated circuits. The on-chip fingerprint circuit does not require additional die area, I/O pins, or a separate read-out circuit. This approach to assuring integrity in the semiconductor supply chain will result in negative financial incentives for counterfeiters. An 80 bit authentication circuit which includes a 16 bit frame header has been designed in a UMC 65nm process with an area estimate of 0.01 mm2. 

   more » « less
4. Counterfeit Mitigation with PUF-Embedded Readout

   Ebenezer, P. (March 2020, Government Microelectronics Applications and Critical Technologies Conference)

   An anticounterfeit strategy based upon PUFembedded authentication circuits is proposed that will eliminate financial incentives for counterfeiters and reduce the insertion barrier for COTS manufactures. In many applications, the authentication circuit will not require additional die area, pins, or a power overhead and will not adversely affect the performance of the original circuitry. The performance of an implementation of the authentication circuit which has a large number of challenge/response pairs has been designed in a UMC 65 nm process will be discussed. 

   more » « less
5. FBAR-BASED SENSOR FOR WIRELESS RFID AUTHENTICATION OF INTEGRATED CIRCUITS

   https://doi.org/10.31438/trf.hh2018.53  

   Shkel, Anton; Barekatain, Matin (June 2018, Technical digest - Solid-State Sensor, Actuator, and Microsystems Workshop)

   This paper describes an integrated circuit (IC) authentication and tamper detection system, based on a Film Bulk Acoustic Resonator (FBAR) and passive Radio-Frequency Identification (RFID), which allows for wireless detection of tampering or counterfeiting in packaged ICs. We demonstrate the concept through the use of a 2.6 GHz FBAR based on a Zinc Oxide (ZnO) thin film. The FBAR is series connected to a piezoelectric energy harvester, which can generate voltage pulses with a peak amplitude of 56 V when tampering activity is detected. Our measurements validate this concept and demonstrate that we can permanently alter the high frequency resonance characteristics of the FBAR through dielectric breakdown caused by tampering. 

   more » « less