Cabrera, Anthony M, Young, Aaron R, Lambert, Jacob, Xiao, Zhili, An, Amy, Lee, Seyong, Jin, Zheming, Kim, Jungwon, Buhler, Jeremy, Chamberlain, Roger D, and Vetter, Jeffrey S. Toward Evaluating High-Level Synthesis Portability and Performance between Intel and Xilinx FPGAs. Retrieved from https://par.nsf.gov/biblio/10283241. Proc. of 9th International Workshop on OpenCL . Web. doi:10.1145/3456669.3456699.

Cabrera, Anthony M, Young, Aaron R, Lambert, Jacob, Xiao, Zhili, An, Amy, Lee, Seyong, Jin, Zheming, Kim, Jungwon, Buhler, Jeremy, Chamberlain, Roger D, & Vetter, Jeffrey S. Toward Evaluating High-Level Synthesis Portability and Performance between Intel and Xilinx FPGAs. Proc. of 9th International Workshop on OpenCL, (). Retrieved from https://par.nsf.gov/biblio/10283241. https://doi.org/10.1145/3456669.3456699

Cabrera, Anthony M, Young, Aaron R, Lambert, Jacob, Xiao, Zhili, An, Amy, Lee, Seyong, Jin, Zheming, Kim, Jungwon, Buhler, Jeremy, Chamberlain, Roger D, and Vetter, Jeffrey S. "Toward Evaluating High-Level Synthesis Portability and Performance between Intel and Xilinx FPGAs". Proc. of 9th International Workshop on OpenCL (). Country unknown/Code not available. https://doi.org/10.1145/3456669.3456699. https://par.nsf.gov/biblio/10283241.

@article{osti_10283241,
place = {Country unknown/Code not available}, title = {Toward Evaluating High-Level Synthesis Portability and Performance between Intel and Xilinx FPGAs}, url = {https://par.nsf.gov/biblio/10283241}, DOI = {10.1145/3456669.3456699}, abstractNote = {}, journal = {Proc. of 9th International Workshop on OpenCL}, author = {Cabrera, Anthony M and Young, Aaron R and Lambert, Jacob and Xiao, Zhili and An, Amy and Lee, Seyong and Jin, Zheming and Kim, Jungwon and Buhler, Jeremy and Chamberlain, Roger D and Vetter, Jeffrey S}, editor = {null} }