This paper presents a voltage multiplier topology that is a hybrid between a Cockcroft-Walton multiplier and a Dickson charge pump. The Cockcroft-Walton structure exhibits significant output voltage drop under load as the number of multiplier stage increases. This is because all coupling capacitors are connected in series. Dickson charge pump mitigates this issue by connecting all capacitors in parallel. But this solution comes at the expense of large capacitor voltage stress at the last multiplier stage. The proposed hybrid structure arranges some capacitors in parallel and others in series, thereby achieving low output voltage drop and low capacitor voltage stress at the same time. We develop a model that predicts hybrid multiplier's performance and validate it experimentally. We also demonstrate a 60 V-to-2.25 kV dc-dc converter based on a 16-stage hybrid voltage multiplier which achieves a voltage gain of 12.8 while keeping the highest capacitor voltage stress to 660 V.
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Low-Ripple High-Voltage DC Generation Using a Serially Segmented Multiphase Voltage Multiplier
This paper presents a voltage multiplier topology that is suitable for a low-ripple high-voltage dc generation. The topology has a number of voltage multipliers connected in series and driven at different phases. Compared to a single-phase multiplier, an n-phase voltage multiplier has an output ripple that is smaller by n times. Since the ripple frequency is simultaneously increased by n times, a simple RC lowpass filter further reduces the ripple amplitude by n times, resulting in ripple reduction of n^2 times. We demonstrate the ripple reduction of the proposed topology using a 6 V-to-800 V power supply with a 16-stage four-phase bipolar voltage multiplier. The output ripple frequency is eight times the converter's switching frequency and the ripple amplitude is significantly smaller than the conventional single-phase voltage multiplier.
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- Award ID(s):
- 1808489
- NSF-PAR ID:
- 10301394
- Date Published:
- Journal Name:
- 2020 IEEE Energy Conversion Congress and Exposition (ECCE)
- Page Range / eLocation ID:
- 962 to 968
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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Summary Inductive power transfer has become an emerging technology for its significant benefits in many applications, including mobile phones, laptops, electric vehicles, implanted bio‐sensors, and internet of things (IoT) devices. In modern applications, a direct current–direct current (DC–DC) converter is one of the essential components to regulate the output supply voltage for achieving the desired characteristics, that is, steady voltage with lower peak ripples. This paper presents a switched‐capacitor (SC) DC–DC converter using complementary architecture to provide a regulated DC voltage with an increased dynamic response. The proposed topology enhances the converter efficiency by decreasing the equivalent output resistance to half by connecting two symmetric SC single ladder converters. The proposed converter is designed using the standard 130‐nm BiCMOS process. The results show that the proposed architecture produces 327‐mV DC output with a rise time of 60.1 ns and consumes 3.449‐nW power for 1.0‐V DC supply. The output settling time is 43.6% lower than the single‐stage SC DC–DC converter with an input frequency of 200 MHz. The comparison results show that the proposed converter has a higher power conversion efficiency of 93.87
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Conference Paper:
- https://doi.org/10.1109/ECCE44975.2020.9235707
