It has been predicted that within the next tenfifteen years, quantum computers will have computational power sufficient to break current public-key cryptography schemes. When that happens, all traditional methods of dealing with the growing computational capabilities of potential attackers, such as increasing key sizes, will be futile. The only viable solution is to develop new standards based on algorithms that are resistant to quantum computer attacks and capable of being executed on traditional computing platforms, such as microprocessors and FPGAs. Leading candidates for new standards include lattice-based post-quantum cryptography (PQC) algorithms. In this paper, we present the results of implementing and benchmarking three lattice-based key encapsulation mechanisms (KEMs) that have progressed to Round 2 of the NIST standardization process. Our implementations are based on a software/hardware codesign approach, which is particularly applicable to the current stage of the NIST PQC standardization process, where the large number and high complexity of the candidates make traditional hardware benchmarking extremely challenging. We propose and justify the choice of a suitable system-on-chip platform and design methodology. The obtained results indicate the potential for very substantial speed-ups vs. purely software implementations, reaching 28x for encapsulation and 20x for decapsulation.
A Monolithic Hardware Implementation of Kyber: Comparing Apples to Apples in PQC Candidates
With the advent of large-scale quantum computers, factoring
and discrete logarithm problems could be solved using the polynomialtime
quantum algorithms. To ensure public-key security, a transition to
quantum-resistant cryptographic protocols is required. Performance of
hardware accelerators targeting different platforms and diverse application
goals plays an important role in PQC candidates’ differentiation.
Hardware accelerators based on FPGAs and ASICs also provide higher
flexibility to create a very low area or ultra-high performance implementations
at the high cost of the other. While the hardware/software codesign
development of PQC schemes has already received an increasing
research effort, a cost analysis of efficient pure hardware implementation
is still lacking. On the other hand, since FPGA has various types of hardware
resources, evaluating and making the accurate and fair comparison
of hardware-based implementations against each other is very challenging.
Without a common foundation, apples are compared to oranges.
This paper demonstrates a pure hardware architecture for Kyber as one
of the finalists in the third round of the NIST post-quantum cryptography
standardization process. To enable real, realistic, and comparable
evaluations in PQC schemes over hardware platforms, we compare our
architecture over the ASIC platform as a common foundation showing
that it outperforms the previous works in the literature.
- Award ID(s):
- 1801341
- Publication Date:
- NSF-PAR ID:
- 10337497
- Journal Name:
- LatinCrypt
- Volume:
- 12912
- Sponsoring Org:
- National Science Foundation
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Accepted Manuscript1.0
- Publisher's Version of Record
- https://doi.org/10.1007/978-3-030-88238-9_6
