In recent years, Quantum Computing (QC) has progressed to the point where small working prototypes are available for use. Termed Noisy Intermediate-Scale Quantum (NISQ) computers, these prototypes are too small for large benchmarks or even for Quantum Error Correction, but they do have sufficient resources to run small benchmarks, particularly if compiled with optimizations to make use of scarce qubits and limited operation counts and coherence times. QC has not yet, however, settled on a particular preferred device implementation technology, and indeed different NISQ prototypes implement qubits with very different physical approaches and therefore widely-varying device and machine characteristics. Our work performs a full-stack, benchmark-driven hardware-software analysis of QC systems. We evaluate QC architectural possibilities, software-visible gates, and software optimizations to tackle fundamental design questions about gate set choices, communication topology, the factors affecting benchmark performance and compiler optimizations. In order to answer key cross-technology and cross-platform design questions, our work has built the first top-to-bottom toolflow to target different qubit device technologies, including superconducting and trapped ion qubits which are the current QC front-runners. We use our toolflow, TriQ, to conduct real-system measurements on 7 running QC prototypes from 3 different groups, IBM, Rigetti, and University of Maryland. From these real-system experiences at QC's hardware-software interface, we make observations about native and software-visible gates for different QC technologies, communication topologies, and the value of noise-aware compilation even on lower-noise platforms. This is the largest cross-platform real-system QC study performed thus far; its results have the potential to inform both QC device and compiler design going forward.
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Toward systematic architectural design of near-term trapped ion quantum computers
Trapped ions (TIs) are a leading candidate for building Noisy Intermediate-Scale Quantum (NISQ) hardware. TI qubits have fundamental advantages over other technologies, featuring high qubit quality, coherence time, and qubit connectivity. However, current TI systems are small in size and typically use a single trap architecture, which has fundamental scalability limitations. To progress toward the next major milestone of 50--100 qubit TI devices, a modular architecture termed the Quantum Charge Coupled Device (QCCD) has been proposed. In a QCCD-based TI device, small traps are connected through ion shuttling. While the basic hardware components for such devices have been demonstrated, building a 50--100 qubit system is challenging because of a wide range of design possibilities for trap sizing, communication topology, and gate implementations and the need to match diverse application resource requirements. Toward realizing QCCD-based TI systems with 50--100 qubits, we perform an extensive application-driven architectural study evaluating the key design choices of trap sizing, communication topology, and operation implementation methods. To enable our study, we built a design toolflow, which takes a QCCD architecture's parameters as input, along with a set of applications and realistic hardware performance models. Our toolflow maps the applications onto the target device and simulates their execution to compute metrics such as application run time, reliability, and device noise rates. Using six applications and several hardware design points, we show that trap sizing and communication topology choices can impact application reliability by up to three orders of magnitude. Microarchitectural gate implementation choices influence reliability by another order of magnitude. From these studies, we provide concrete recommendations to tune these choices to achieve highly reliable and performant application executions. With industry and academic efforts underway to build TI devices with 50-100 qubits, our insights have the potential to influence QC hardware in the near future and accelerate the progress toward practical QC systems.
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- NSF-PAR ID:
- 10378389
- Date Published:
- Journal Name:
- Communications of the ACM
- Volume:
- 65
- Issue:
- 3
- ISSN:
- 0001-0782
- Page Range / eLocation ID:
- 101 to 109
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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Abstract We propose a new scalable platform for quantum computing (QC)—an array of optically trapped symmetric-top molecules (STMs) of the alkaline earth monomethoxide (MOCH3) family. Individual STMs form qubits, and the system is readily scalable to 100–1000 qubits. STM qubits have desirable features for QC compared to atoms and diatomic molecules. The additional rotational degree of freedom about the symmetric-top axis gives rise to closely spaced opposite parity
K -doublets that allow full alignment at low electric fields, and the hyperfine structure naturally provides magnetically insensitive states with switchable electric dipole moments. These features lead to much reduced requirements for electric field control, provide minimal sensitivity to environmental perturbations, and allow for 2-qubit interactions that can be switched on at will. We examine in detail the internal structure of STMs relevant to our proposed platform, taking into account the full effective molecular Hamiltonian including hyperfine interactions, and identify useable STM qubit states. We then examine the effects of the electric dipolar interaction in STMs, which not only guide the design of high-fidelity gates, but also elucidate the nature of dipolar exchange in STMs. Under realistic experimental parameters, we estimate that the proposed QC platform could yield gate errors at the 10−3level, approaching that required for fault-tolerant QC. -
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.1145/3511064
