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This content will become publicly available on September 19, 2023

Title: A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm
We present a generic and programmable Processing-in-SRAM (PSRAM) accelerator chip design based on an 8T-SRAM array to accommodate a complete set of Boolean logic operations (e.g., NOR/NAND/XOR, both 2- and 3-input), majority, and full adder, for the first time, all in a single cycle. PSRAM provides the programmability required for in-memory computing platforms that could be used for various applications such as parallel vector operation, neural networks, and data encryption. The prototype design is implemented in a SRAM macro with size of 16 kb, demonstrating one of the fastest programmable in-memory computing system to date operating at 1.23 GHz. The 65nm prototype chip achieves system-level peak throughput of 1.2 TOPS, and energy-efficiency of 34.98 TOPS/W at 1.2V.
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Award ID(s):
2144751 2003749
Publication Date:
Journal Name:
2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)
Page Range or eLocation-ID:
153 to 156
Sponsoring Org:
National Science Foundation
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