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1. Design Techniques for a Multi-Phase Injection-Based Eight-Phase 17-GHz Clock Generator for Multi-Phase Wireline Receivers

   https://doi.org/10.1109/TCSI.2025.3563517  

   Zhou, Bob; Nikolić, Borivoje (January 2025, IEEE Transactions on Circuits and Systems I: Regular Papers)

   NA (Ed.)

   Clock generation for high-speed wireline receivers must provide multiple clock phases with high-resolution rotation. To address this, an 8-phase 17 GHz clock generation circuit with built-in 6b rotation is presented. Multi-phase injection is used to perform reference-side phase rotation to efficiently generate and rotate eight clock phases. The injection method is analyzed with a model to study the introduced nonlinearity, and the effect of the injection strength is discussed. Designed by using BAG3++ for layout-aware design optimization, the proposed circuit achieves 98 fs RMS jitter and a measured DNLpp and INLpp of 1.26 and 4.05 LSB respectively, while consuming 33 mW. 

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2. A 60-GHz Digital Sub-Sampling Integer-N Phase-Locked Loop

   https://doi.org/10.1109/WMCS49442.2020.9172416  

   Rong, Chao; Mondal, Susnata; Carley, L. Richard; Paramesh, Jeyanandh (May 2020, 2020 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS))

   null (Ed.)

   Digital phase-locked loops (DPLL) are finding new applications in highly demanding contexts such as frequency synthesis for millimeter-wave (mm-wave) communications and clock generation for ultra-high-speed wireline transceivers. In a typical DPLL, however, a time-to-digital converter (TDC) with fine time resolution, high linearity and high dynamic range is required to meet stringent noise and spur performance requirements, which negatively impacts the power consumption in a DPLL. A bang-bang phase-detector (BBPD) outperforms a multi-bit TDC in terms of its’ jitter-power tradeoff, but its’ highly non-linear phase detection characteristic limits the locking speed of the loop. This research explores the design and of a 60 GHz digital sub-sampling phase-locked loop that uses a BBPD loop for frequency tracking and a coarse TDC loop for fast frequency acquisition. A prototype of the DPLL is designed in a 28-nm CMOS technology with supporting evidence through extensive simulations. 

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3. Byzantine-Tolerant Phase Clock

   https://doi.org/10.4230/lipics.opodis.2025.30  

   Busch, Costas; Garncarek, Paweł; Kowalski, Dariusz R (January 2026, Schloss Dagstuhl – Leibniz-Zentrum für Informatik)

   Arusoaie, Andrei; Onica, Emanuel; Spear, Michael; Tucci-Piergiovanni, Sara (Ed.)

   A phase clock is a basic synchronization mechanism that keeps distributed nodes closely synchronized to execute the same phase of a distributed algorithm. A phase clock is typically implemented with a local logical counter that keeps track of the current phase count. Phase clocks are particularly useful in population protocols for implementing leader election and majority selection. We study phase clocks that tolerate Byzantine faults. We show that there is a phase clock that tolerates up to f < n/3 faulty nodes, where n is the number of nodes, such that the gap of the local counter values is O(n²log n). The gap can be further lowered to O(log n) when f ≤ n/8. We also show that if f > n/3, then the gap grows to infinity as time increases. While analyzing phase clock we introduce novel techniques and bounds for balls into bins processes, which might be of independent interest. Using the phase clock, we obtain a majority selection population protocol that tolerates up to f faults and decides on the majority value in O(log² n) parallel time using poly-log states per node. 

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4. A multi-mass and multi-hit two-camera 3D ion momentum imaging system

   https://doi.org/10.1063/5.0220000  

   Orunesajo, Emmanuel; Abubakar, Sulaiman; Oguh, Blessed; Lee, Suk Kyoung; Li, Wen (July 2024, Review of Scientific Instruments)

   We demonstrate an improved two-camera system for multi-mass and multi-hit three-dimensional (3D) momentum imaging of ions. The imaging system employs two conventional complementary metal–oxide–semiconductor cameras. We have shown previously that the system can time slice ion Newton spheres with a time resolution of 8.8 ns, limited by camera timing jitter [J. Chem. Phys., 158, 191104 (2023)]. In this work, a jitter correction method was developed to suppress the camera jitter and improve the time resolution to better than 2 ns. With this resolution, full 3D momentum distributions of ions can be obtained. We further show that this method can detect two ions with different masses when utilizing both the rising and falling edges of the cameras. 

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5. Learning-based Phase-aware Multi-core CPU Workload Forecasting

   https://doi.org/10.1145/3564929  

   Alcorta, Erika S.; Gerstlauer, Andreas (December 2022, ACM Transactions on Design Automation of Electronic Systems)

   Predicting workload behavior during workload execution is essential for dynamic resource optimization in multi-processor systems. Recent studies have proposed advanced machine learning techniques for dynamic workload prediction. Workload prediction can be cast as a time series forecasting problem. However, traditional forecasting models struggle to predict abrupt workload changes. These changes occur because workloads are known to go through phases. Prior work has investigated machine learning-based approaches for phase detection and prediction, but such approaches have not been studied in the context of dynamic workload forecasting. In this paper, we propose phase-aware CPU workload forecasting as a novel approach that applies long-term phase prediction to improve the accuracy of short-term workload forecasting. Phase-aware forecasting requires machine learning models for phase classification, phase prediction, and phase-based forecasting that have not been explored in this combination before. Furthermore, existing prediction approaches have only been studied in single-core settings. This work explores phase-aware workload forecasting with multi-threaded workloads running on multi-core systems. We propose different multi-core settings differentiated by the number of cores they access and whether they produce specialized or global outputs per core. We study various advanced machine learning models for phase classification, phase prediction, and phase-based forecasting in isolation and different combinations for each setting. We apply our approach to forecasting of multi-threaded Parsec and SPEC workloads running on an 8-core Intel Core-i9 platform. Our results show that combining GMM clustering with LSTMs for phase prediction and phase-based forecasting yields the best phase-aware forecasting results. An approach that uses specialized models per core achieves an average error of 23% with up to 22% improvement in prediction accuracy compared to a phase-unaware setup. 

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