A unique confined lateral selective epitaxial growth (CLSEG) [1] technique for next generation semiconductor devices was demonstrated in [2, 3] and termed template assisted selective epitaxy (TASE). This technique is based on the formation of hollow confined structures that drive subsequent growth initiation only from a small area of the substrate exposed to the growth environment, dubbed a seed, and continued growth is forced within the template. This allows to arbitrarily determine the shape and orientation of the grown material and to form novel nano-electronic device structures.
Here, results are reported on the fabrication of channel-like nanometer sized horizontal structures, and, the subsequent homoepitaxy of indium phosphide (InP) to demonstrate the potential for TASE to create vertical heterojunctions that could enable the next generation of tunnel field-effect transistors (TFETs) [4].
Templates were fabricated with a combination of e-beam lithography, PECVD deposition, resist patterning, and selective wet etches, on (100) n-type InP wafers. Homoepitaxy was done via MOVPE achieving growth selectivity with a growth temperature of 640°C, group III precursor molar rate of 4E-6 mol/min, a V/III ratio of 400. Trimethylindium (TMIn) and tertiarybutylphosphine (TBP) are used as indium and phosphorus precursors respectively.
Characterization via scanning electron microscopy (SEM) and transmission electron microscopy (TEM) was employed to determine the success of growth in the template, initiation at the “seed”, area selectivity, faceting at the growth front, and conformality to the template.
Each die consisted in a parametric array of structures of varying characteristic sizes that allows, via growth-interrupt trials, to analyze confined growth behavior and how this deviates from bulk epitaxy. Initial data suggests growth rate suppression with increased channel length. MOVPE in these conditions is known to be mass transport limited [5], so this could be explained with the need for the precursors to diffusively cover longer distances.
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Towards Horizontal Heterojunctions for Tunnel Field Effect Transistors with Template Assisted Selective Epitaxy via MOCVD
Tunneling field effect transistors (TFETs) have gained much interest in the previous decade for use in low power CMOS electronics due to their sub-thermal switching [1]. To date, all TFETs are fabricated as vertical nanowires or fins with long, difficult processes resulting in long learning cycle and incompatibility with modern CMOS processing. Because most TFETs are heterojunction TFETs (HJ-TFETs), the geometry of the device is inherently vertically because dictated by the orientation of the tunneling HJ, achieved by typical epitaxy.
Template assisted selective epitaxy was demonstrated for vertical nanowires [2] and horizontally arranged nanorods [3] for III-V on Si integration. In this work, we report results on the area selective and template assisted epitaxial growth of InP, utilizing SiO2 based confined structures on InP substrates, which enables horizontal HJs, that can find application in the next generation of TFET devices. The geometries of the confined structures used are so that only a small area of the InP substrate, dubbed seed, is visible to the growth atmosphere. Growth is initiated selectively only at the seed and then proceeds in the hollow channel towards the source hole. As a result, growth resembles epitaxial lateral overgrowth from a single nucleation point [4], reaping the benefits of defect confinement and, contrary to spontaneous nanowire growth, allows orientation in an arbitrary, template defined direction.
Indium phosphide 2-inch (110) wafers are used as the starting substrate. The process flow (Fig.1) consists of two plasma enhanced chemical vapor deposition (PECVD) steps of SiO2, appropriately patterned with electron beam lithography (EBL), around a PECVD amorphous silicon sacrificial layer. The sacrificial layer is ultimately wet etched with XeF2 to form the final, channel like template. Not shown in the schematic in Fig.1 is an additional, ALD deposited, 3 nm thick, alumina layer which prevents plasma damage to the starting substrate and is removed via a final tetramethylammonium hydroxide (TMAH) based wet etch. As-processed wafers were then diced and loaded in a Thomas Swan Horizontal reactor. Successful growth conditions found were 600°C with 4E6 mol/min of group III precursor, a V/III ratio of 400 and 8 lpm of hydrogen as carrier gas. Trimethylindium (TMIn) and tertiarybutylphosphine (TBP) were used as In and P precursors respectively. Top view SEM (Fig.2) confirms growth in the template thanks to sufficient Z-contrast despite the top oxide layer, not removed before imaging. TEM imaging shows a cross section of the confined structure taken at the seed hole (Fig.3). The initial growth interface suggests growth was initiated at the seed hole and atomic order of the InP conforms to the SiO2 template both at the seed and at the growth front. A sharp vertical facet is an encouraging result for the future development of vertical HJ based III-V semiconductor devices.
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- Award ID(s):
- 1640030
- NSF-PAR ID:
- 10114094
- Date Published:
- Journal Name:
- International conference on MOVPE
- Volume:
- NA
- Issue:
- NA
- Page Range / eLocation ID:
- NA
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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