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Abstract Source/Drain extension doping is crucial for minimizing the series resistance of the ungated channel and reducing the contact resistance of field‐effect transistors (FETs) in complementary metal–oxide–semiconductor (CMOS) technology. 2D semiconductors, such as MoS2and WSe2, are promising channel materials for beyond‐silicon CMOS. A key challenge is to achieve extension doping for 2D monolayer FETs without damaging the atomically thin material. This work demonstrates extension doping with low‐resistance contacts for monolayer WSe2p‐FETs. Self‐limiting oxidation transforms a bilayer WSe2into a hetero‐bilayer of a high‐work‐function WOxSeyon a monolayer WSe2. Then, damage‐free nanolithography defines an undoped nano‐channel, preserving the high on‐current of WOxSey‐doped FETs while significantly improving their on/off ratio. The insertion of an amorphous WOxSeyinterlayer under the contacts achieves record‐low contact resistances for monolayer WSe2over a hole density range of 1012to 1013cm−2(1.2 ± 0.3 kΩ µm at 1013cm−2). The WOxSey‐doped extension exhibits a sheet resistance as low as 10 ± 1 kΩ □−1. Monolayer WSe2p‐FETs with sub‐50 nm channel lengths reach a maximum drain current of 154 µA µm−1with an on/off ratio of 107–108. These results define strategies for nanometer‐scale selective‐area doping in 2D FETs and other 2D architectures.
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Improvements in 2D p-type WSe2 transistors towards ultimate CMOS scaling
Abstract This paper provides comprehensive experimental analysis relating to improvements in the two-dimensional (2D) p-type metal–oxide–semiconductor (PMOS) field effect transistors (FETs) by pure van der Waals (vdW) contacts on few-layer tungsten diselenide (WSe 2 ) with high-k metal gate (HKMG) stacks. Our analysis shows that standard metallization techniques (e.g., e-beam evaporation at moderate pressure ~ 10 –5 torr) results in significant Fermi-level pinning, but Schottky barrier heights (SBH) remain small (< 100 meV) when using high work function metals (e.g., Pt or Pd). Temperature-dependent analysis uncovers a more dominant contribution to contact resistance from the channel access region and confirms significant improvement through less damaging metallization techniques (i.e., reduced scattering) combined with strongly scaled HKMG stacks (enhanced carrier density). A clean contact/channel interface is achieved through high-vacuum evaporation and temperature-controlled stepped deposition providing large improvements in contact resistance. Our study reports low contact resistance of 5.7 kΩ-µm, with on-state currents of ~ 97 µA/µm and subthreshold swing of ~ 140 mV/dec in FETs with channel lengths of 400 nm. Furthermore, theoretical analysis using a Landauer transport ballistic model for WSe 2 SB-FETs elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance (excellent on-state current vs subthreshold swing benchmarks) towards the ultimate CMOS scaling limit.
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- PAR ID:
- 10426198
- Date Published:
- Journal Name:
- Scientific Reports
- Volume:
- 13
- Issue:
- 1
- ISSN:
- 2045-2322
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript
- Journal Article:
- https://doi.org/10.1038/s41598-023-30317-4
