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1. Extension Doping with Low‐Resistance Contacts for P‐Type Monolayer WSe ₂ Field‐Effect Transistors

   https://doi.org/10.1002/aelm.202400843  

   Chen, Sihan; Zhang, Yue; King, William P; Bashir, Rashid; van_der_Zande, Arend M (December 2024, Advanced Electronic Materials)

   Abstract Source/Drain extension doping is crucial for minimizing the series resistance of the ungated channel and reducing the contact resistance of field‐effect transistors (FETs) in complementary metal–oxide–semiconductor (CMOS) technology. 2D semiconductors, such as MoS₂and WSe₂, are promising channel materials for beyond‐silicon CMOS. A key challenge is to achieve extension doping for 2D monolayer FETs without damaging the atomically thin material. This work demonstrates extension doping with low‐resistance contacts for monolayer WSe₂p‐FETs. Self‐limiting oxidation transforms a bilayer WSe₂into a hetero‐bilayer of a high‐work‐function WO_xSe_yon a monolayer WSe₂. Then, damage‐free nanolithography defines an undoped nano‐channel, preserving the high on‐current of WO_xSe_y‐doped FETs while significantly improving their on/off ratio. The insertion of an amorphous WO_xSe_yinterlayer under the contacts achieves record‐low contact resistances for monolayer WSe₂over a hole density range of 10¹²to 10¹³cm⁻²(1.2 ± 0.3 kΩ µm at 10¹³cm⁻²). The WO_xSe_y‐doped extension exhibits a sheet resistance as low as 10 ± 1 kΩ □⁻¹. Monolayer WSe₂p‐FETs with sub‐50 nm channel lengths reach a maximum drain current of 154 µA µm⁻¹with an on/off ratio of 10⁷–10⁸. These results define strategies for nanometer‐scale selective‐area doping in 2D FETs and other 2D architectures. 

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2. Analysis and EOT Scaling on Top‐ and Double‐Gate 2D CVD‐Grown Monolayer MoS ₂ FETs

   https://doi.org/10.1002/aelm.202400152  

   Patoary, Naim Hossain; Mamun, Fahad Al; Xie, Jing; Grasser, Tibor; Sanchez_Esqueda, Ivan (November 2024, Advanced Electronic Materials)

   Abstract 2D layered semiconductors have attracted considerable attention for beyond‐Si complementary metal‐oxide‐semiconductor (CMOS) technologies. They can be prepared into ultrathin channel materials toward ultrascaled device architectures, including double‐gate field‐effect‐transistors (DGFETs). This work presents an experimental analysis of DGFETs constructed from chemical vapor deposition (CVD)‐grown monolayer (1L) molybdenum disulfide (MoS₂) with atomic layer deposition (ALD) of hafnium oxide (HfO₂) high‐k gate dielectrics (top and bottom). This extends beyond previous studies of DGFETs based mostly on exfoliated (few‐nm thick) MoS₂flakes, and advances toward large‐area wafer‐scale processing. Here, significant improvements in performance are obtained with DGFETs (i.e., improvements in ON/OFF ratio, ON‐state current, sub‐threshold swing, etc.) compared to single top‐gate FETs. In addition to multi‐gate device architectures (e.g., DGFETs), the scaling of the equivalent oxide thickness (EOT) is crucial toward improved electrostatics required for next‐generation transistors. However, the impact of EOT scaling on the characteristics of CVD‐grown MoS₂DGFETs remains largely unexplored. Thus, this work studies the impact of EOT scaling on subthreshold swing (SS) and gate hysteresis using current–voltage (I–V) measurements with varying sweep rates. The experimental analysis and results elucidate the basic mechanisms responsible for improvements in CVD‐grown 1L‐MoS₂DGFETs compared to standard top‐gate FETs. 

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3. Enhanced carrier transport by transition metal doping in WS 2 field effect transistors

   https://doi.org/10.1039/d0nr01573c  

   Liu, Maomao; Wei, Sichen; Shahi, Simran; Jaiswal, Hemendra Nath; Paletti, Paolo; Fathipour, Sara; Remškar, Maja; Jiao, Jun; Hwang, Wansik; Yao, Fei; et al (August 2020, Nanoscale)

   null (Ed.)

   High contact resistance is one of the primary concerns for electronic device applications of two-dimensional (2D) layered semiconductors. Here, we explore the enhanced carrier transport through metal–semiconductor interfaces in WS 2 field effect transistors (FETs) by introducing a typical transition metal, Cu, with two different doping strategies: (i) a “generalized” Cu doping by using randomly distributed Cu atoms along the channel and (ii) a “localized” Cu doping by adapting an ultrathin Cu layer at the metal–semiconductor interface. Compared to the pristine WS 2 FETs, both the generalized Cu atomic dopant and localized Cu contact decoration can provide a Schottky-to-Ohmic contact transition owing to the reduced contact resistances by 1–3 orders of magnitude, and consequently elevate electron mobilities by 5–7 times. Our work demonstrates that the introduction of transition metal can be an efficient and reliable technique to enhance the carrier transport and device performance in 2D TMD FETs. 

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4. Contact Length Scaling in In2O3 and InGaZnO FETs: Critical Roles of Quantum Confinement and Indium Concentration Tuning

   https://doi.org/10.1109/TED.2025.3649612  

   Lin, Jian-Yu; Niu, Chang; Lin, Zehao; Lee, Sumi; Liu, Chang; Lu, Juanjuan; Wang, Haiyan; Ye, Peide D (February 2026, IEEE Transactions on Electron Devices)

   This work presents a systematic study of contact length (LC) scaling in ultrathin In2O3 and InGaZnO field-effect transistors (FETs), focusing on strategies to achieve low contact resistance (RC) at aggressively scaled contacted gate pitches (CGP). Through transfer length method (TLM) analysis, we extract the RC, transfer length (LT), and contact resistivity (ρC) in devices with varying channel thicknesses (Tch) and indium concentrations. In2O3 FETs with increased Tch from 1.2 nm to 2.0 nm exhibit substantial improvements in contact properties, with LT reduced from 67.5 nm to 30.4 nm, RC0 from 302.6 to 195.7 Ω·µm, and ρC from 1.35×10⁻⁶ to 7.94×10⁻⁸ Ω·cm². Similarly, InGaZnO FETs with higher indium concentration show enhanced contact behavior approaching that of In2O3. The observed trends are explained by EC–Charge neutrality level (CNL) band alignment models, which attribute these contact improvements to Schottky barrier height (ΦSB) lowering via quantum confinement and indium composition tuning. Leveraging these insights, we demonstrate aggressively scaled In2O3 FETs with LC = Lch = 40 nm and CGP = 80 nm, achieving low RC = 140.4 Ω·µm and high maximum drain current (Imax) of 1.57 mA/µm. These results underscore the importance of band structure engineering for contact optimization in oxide semiconductors and provide a pathway toward high-performance, nanoscale devices for monolithic 3D integration. 

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5. Wafer-scale 2D MoS₂ transistors with sub-5 nm channel length and subthreshold performance beyond the silicon limit

   https://doi.org/10.1038/s41467-026-77186-9  

   Lin, S; Huang, T; Yang, N; Zheng, X; Yang, H; Yun, H S; Turner, G; Zhong, Y; Zou, J; Zhang, K; et al (September 2026, Nature Communications)

   The downscaling of silicon field-effect transistors is approaching fundamental limits, with the international roadmap for devices and systems (IRDS) projecting a 12 nm channel length plateau by 2037. Two-dimensional (2D) semiconductors have emerged as promising candidates for extended transistor scaling. However, no experimental demonstration has thus far surpassed the fundamental switching limits of advanced silicon. Here, we report monolayer MoS₂ transistors with physical channel lengths below 5 nm, achieving a subthreshold swing of 88 mV/dec and an on/off ratio above 106. These results surpass both the theoretical subthreshold limit of silicon and state-of-the-art emerging semiconductors-based transistors at comparable dimensions. To ensure high throughput, we develop a photolithography based, complementary metal oxide semiconductor (CMOS) compatible process and demonstrate 4-inch wafer-scale integration. We implement a design–technology co-optimization approach featuring an air-gap isolation and gate-contact overlap design to effectively suppress short channel effects. This work demonstrates subthreshold transport in a 2D semiconductor transistor beyond the silicon limit, showing a viable pathway for extending transistor scaling and energy-efficient computing. 

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