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While magnetoresistive random-access memory (MRAM) stands out as a leading candidate for embedded nonvolatile memory and last-level cache applications, its endurance is compromised by substantial self-heating due to the high programming current density. The effect of self-heating on the endurance of the magnetic tunnel junction (MTJ) has primarily been studied in spin-transfer torque (STT)-MRAM. Here, we analyze the transient temperature response of two-terminal spin–orbit torque (SOT)-MRAM with a 1 ns switching current pulse using electro-thermal simulations. We estimate a peak temperature range of 350–450 °C in 40 nm diameter MTJs, underscoring the critical need for thermal management to improve endurance. We suggest several thermal engineering strategies to reduce the peak temperature by up to 120 °C in such devices, which could improve their endurance by at least a factor of 1000× at 0.75 V operating voltage. These results suggest that two-terminal SOT-MRAM could significantly outperform conventional STT-MRAM in terms of endurance, substantially benefiting from thermal engineering. These insights are pivotal for thermal optimization strategies in the development of MRAM technologies.

 

Due to the separate memory and computation units in traditional Von-Neumann architecture, massive data transfer dominates the overall computing system’s power and latency, known as the ‘Memory-Wall’ issue. Especially with ever-increasing deep learning-based AI model size and computing complexity, it becomes the bottleneck for state-of-the-art AI computing systems. To address this challenge, In-Memory Computing (IMC) based Neural Network accelerators have been widely investigated to support AI computing within memory. However, most of those works focus only on inference. The on-device training and continual learning have not been well explored yet. In this work, for the first time, we introduce on-device continual learning with STT-assisted-SOT (SAS) Magnetic Random Access Memory (MRAM) based IMC system. On the hardware side, we have fabricated a SAS-MRAM device prototype with 4 Magnetic Tunnel Junctions (MTJ, each at 100nm × 50nm) sharing a common heavy metal layer, achieving significantly improved memory writing and area efficiency compared to traditional SOT-MRAM. Next, we designed fully digital IMC circuits with our SAS-MRAM to support both neural network inference and on-device learning. To enable efficient on-device continual learning for new task data, we present an 8-bit integer (INT8) based continual learning algorithm that utilizes our SAS-MRAM IMC-supported bit-serial digital in-memory convolution operations to train a small parallel reprogramming Network (Rep-Net) while freezing the major backbone model. Extensive studies have been presented based on our fabricated SAS-MRAM device prototype, cross-layer device-circuit benchmarking and simulation, as well as the on-device continual learning system evaluation. 

As an emerging nonvolatile memory technology, HfO₂‐based ferroelectrics exhibit excellent compatibility with silicon CMOS process flows; however, the reliability of polarization switching in these materials remains a major challenge. During repeated field programming and erase of the polarization state of initially pristine HfO₂‐based ferroelectric capacitors, the magnitude of the measured polarization increases, a phenomenon known as “wake‐up”. In this study, the authors attempt to understand what causes the wake‐up effect in Hf_0.5Zr_0.5O₂(HZO) capacitors using nondestructive methods that probe statistically significant sample volumes. Synchrotron X‐ray diffraction reveals a concerted shift in HZO Bragg peak position as a function of polarization switching cycle number in films prepared under conditions such that they exhibit extremely large (≈3000%) wake‐up. In contrast, a control sample with insignificant wake‐up shows no such peak shift. Capacitance – voltage measurements show evolution in the capacitance loop with switching cycle number for the wake‐up sample and no change for the control sample. Piezoresponse force microscopy measurements are utilized to visualize the domain switching with wake‐up. The combination of these observations clearly demonstrates that wake‐up is caused by a field‐driven phase transformation of the tetragonal phase to the metastable ferroelectric orthorhombic phase during polarization switching of HZO capacitors.

 

Nowadays, research topics on AI accelerator designs have attracted great interest, where accelerating Deep Neural Network (DNN) using Processing-in-Memory (PIM) platforms is an actively-explored direction with great potential. PIM platforms, which simultaneously aims to address power- and memory-wall bottlenecks, have shown orders of performance enhancement in comparison to the conventional computing platforms with Von-Neumann architecture. As one direction of accelerating DNN in PIM, resistive memory array (aka. crossbar) has drawn great research interest owing to its analog current-mode weighted summation operation which intrinsically matches the dominant Multiplication-and-Accumulation (MAC) operation in DNN, making it one of the most promising candidates. An alternative direction for PIM-based DNN acceleration is through bulk bit-wise logic operations directly performed on the content in digital memories. Thanks to the high fault-tolerant characteristic of DNN, the latest algorithmic progression successfully quantized DNN parameters to low bit-width representations, while maintaining competitive accuracy levels. Such DNN quantization techniques essentially convert MAC operation to much simpler addition/subtraction or comparison operations, which can be performed by bulk bit-wise logic operations in a highly parallel fashion. In this paper, we build a comprehensive evaluation framework to quantitatively compare and analyze aforementioned PIM based analog and digital approaches for DNN acceleration. 

Ferroelectric switching is demonstrated in CeO₂‐doped Hf_0.5Zr_0.5O₂(HZCO) thin films with application in back‐end‐of‐line compatible embedded memories. At low cerium oxide doping concentrations (2.0–5.6 mol%), the ferroelectric orthorhombic phase is stabilized after annealing at temperatures below 400 °C. HZCO ferroelectrics show reliable switching characteristics beyond 10¹¹cycles in TiN/HZCO/TiN capacitors, several orders of magnitude greater than identically processed Hf_0.5Zr_0.5O₂(HZO) capacitors, without sacrificing polarization and retention. Internal photoemission and photoconductivity experiments show that CeO₂‐doping introduces in‐gap states in HZCO that are nearly aligned with TiN Fermi level, facilitating electron injection through these states. The enhanced average bulk conduction, which may lead to more uniform thermal dissipation in the HZCO films, delays irreversible degradation via breakdown that leads to device failure after repeated programming cycles.