skip to main content


Title: A New High Step-Up DC-DC Topology with Zero DC Magnetizing Inductance Current and Continuous Input Current
A new high-voltage-gain non-isolated dc-dc topology for applications in renewable energies is proposed. A coupled inductor with three windings is used to increase the proposed topology voltage gain. In addition to increasing the voltage gain, the proposed topology also has other prominent features including continuous input current and zero dc magnetizing inductance current, which reduces the losses and size of coupled inductor core. Furthermore, the continuous input current guarantees a low-volume input filter, which is essential for renewable energy applications. The leakage inductor stored energy is recycled via the diode and capacitor and transferred to the converter output for increasing the efficiency and reducing voltage stresses on the converter components.  more » « less
Award ID(s):
1724227
NSF-PAR ID:
10288505
Author(s) / Creator(s):
; ; ; ;
Date Published:
Journal Name:
2020 IEEE Applied Power Electronics Conference and Exposition (APEC)
Page Range / eLocation ID:
2260 to 2264
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
More Like this
  1. null (Ed.)
    A high-voltage-gain dc-dc converter topology is proposed for renewable energy applications. The proposed coupled-inductor-based high-gain dc-dc converter features reduced input current ripple. The semiconductor elements voltage spikes due to the leakage inductance are prevented through the use of a clamping circuit. The Clamping circuit helps recover the leakage inductance stored energy, which causes voltage spikes on the switch. This results in the selection of elements with lower voltage ratings. Power switches with lower voltage ratings lead to lower conduction losses and improved system efficiency. The DC component of the inductor magnetizing current is zero. Consequently, no energy is stored in the inductor core, and the losses are further reduced. 
    more » « less
  2. In this study, a power converter topology and control schemes for the power converter stages are proposed for a DC extreme fast charger. The proposed system is composed of a cascaded H-bridge (CHB) converter as the active front end (AFE), and an input series output parallel (ISOP), which includes three parallel connected dual active bridge (DAB) cells. A modified Lyapunov Function (LF) based control strategy is applied to obtain high current control response for the AFE. An additional controller to remove the voltage unbalances among the H-bridges is also presented. Additionally, the triple phase-shift (TPS) control method is applied for the ISOP DAB converter. A Lagrange Multiplier (LM) based optimization study is performed to minimize the RMS current of the transformer. The performance of the proposed converter topology and control strategies is validated with MATLAB/Simulink simulations. 
    more » « less
  3. Summary

    Inductive power transfer has become an emerging technology for its significant benefits in many applications, including mobile phones, laptops, electric vehicles, implanted bio‐sensors, and internet of things (IoT) devices. In modern applications, a direct current–direct current (DC–DC) converter is one of the essential components to regulate the output supply voltage for achieving the desired characteristics, that is, steady voltage with lower peak ripples. This paper presents a switched‐capacitor (SC) DC–DC converter using complementary architecture to provide a regulated DC voltage with an increased dynamic response. The proposed topology enhances the converter efficiency by decreasing the equivalent output resistance to half by connecting two symmetric SC single ladder converters. The proposed converter is designed using the standard 130‐nm BiCMOS process. The results show that the proposed architecture produces 327‐mV DC output with a rise time of 60.1 ns and consumes 3.449‐nW power for 1.0‐V DC supply. The output settling time is 43.6% lower than the single‐stage SC DC–DC converter with an input frequency of 200 MHz. The comparison results show that the proposed converter has a higher power conversion efficiency of 93.87%and a lower power density of 0.57 mW/mm2compared to the existing works.

     
    more » « less
  4. null (Ed.)
    This paper presents the integration of an AC-DC rectifier and a DC-DC boost converter circuit designed in 180 nm CMOS process for ultra-low frequency (<; 10 Hz) energy harvesting applications. The proposed rectifier is a very low voltage CMOS rectifier circuit that rectifies the low-frequency signal of 100-250 mV amplitude and 1-10 Hz frequency into DC voltage. In this work, the energy is harvested from the REWOD (reverse electrowetting-on-dielectric) generator, which is a reverse electrowetting technique that converts mechanical vibrations to electrical energy. The objective is to develop a REWOD-based self-powered motion (such as walking, running, jogging, etc.) tracking sensors that can be worn, thus harvesting energy from regular activities. To this end, the proposed circuits are designed in such a way that the output from the REWOD is rectified and regulated using a DC-DC converter which is a 5-stage cross-coupled switching circuit. Simulation results show a voltage range of 1.1 V-2.1 V, i.e., 850-1200% voltage conversion efficiency (VCE) and 30% power conversion efficiency (PCE) for low input signal in the range 100-250 mV in the low-frequency range. This performance verifies the integration of the rectifier and DC-DC boost converter which makes it highly suitable for various motion-based energy harvesting applications. 
    more » « less
  5. With the increasing complexity of highly integrated system on chips (SoCs), the power management system (PMS) is required to provide several power supplies efficiently for individual blocks. This paper presents a single-inductor multiple outputs (SIMO) an inductor-first hybrid converter that generates three outputs between 0.4V and 1.6V from a 1.8V input. The proposed multiple-output hybrid power stage can improve the conversion efficiency by reducing inductor current while extending the output voltage range compared with the existing hybrid topologies. In addition, the proposed converter employs an on-chip switched-capacitor power stage (SCPS) with a dual switching frequency technique, resulting in a fast response time, low cross-regulation, and reduced number of on-chip pads. Measurement results show that the converter achieves a peak efficiency of 87.5% with a maximum output current of 450mA. The converter is integrated with a fast voltage regulation loop with a 500MHz system clock to achieve less than 0.01mA/mV cross-regulation and a maximum 20mV overshoot at full-load transient response. The design is fabricated in the standard 180nm CMOS technology 
    more » « less