An official website of the United States government
Abstract Source/Drain extension doping is crucial for minimizing the series resistance of the ungated channel and reducing the contact resistance of field‐effect transistors (FETs) in complementary metal–oxide–semiconductor (CMOS) technology. 2D semiconductors, such as MoS2and WSe2, are promising channel materials for beyond‐silicon CMOS. A key challenge is to achieve extension doping for 2D monolayer FETs without damaging the atomically thin material. This work demonstrates extension doping with low‐resistance contacts for monolayer WSe2p‐FETs. Self‐limiting oxidation transforms a bilayer WSe2into a hetero‐bilayer of a high‐work‐function WOxSeyon a monolayer WSe2. Then, damage‐free nanolithography defines an undoped nano‐channel, preserving the high on‐current of WOxSey‐doped FETs while significantly improving their on/off ratio. The insertion of an amorphous WOxSeyinterlayer under the contacts achieves record‐low contact resistances for monolayer WSe2over a hole density range of 1012to 1013cm−2(1.2 ± 0.3 kΩ µm at 1013cm−2). The WOxSey‐doped extension exhibits a sheet resistance as low as 10 ± 1 kΩ □−1. Monolayer WSe2p‐FETs with sub‐50 nm channel lengths reach a maximum drain current of 154 µA µm−1with an on/off ratio of 107–108. These results define strategies for nanometer‐scale selective‐area doping in 2D FETs and other 2D architectures.
more »
« less
Improvements in 2D p-type WSe2 transistors towards ultimate CMOS scaling
Abstract This paper provides comprehensive experimental analysis relating to improvements in the two-dimensional (2D) p-type metal–oxide–semiconductor (PMOS) field effect transistors (FETs) by pure van der Waals (vdW) contacts on few-layer tungsten diselenide (WSe2) with high-k metal gate (HKMG) stacks. Our analysis shows that standard metallization techniques (e.g., e-beam evaporation at moderate pressure ~ 10–5 torr) results in significant Fermi-level pinning, but Schottky barrier heights (SBH) remain small (< 100 meV) when using high work function metals (e.g., Pt or Pd). Temperature-dependent analysis uncovers a more dominant contribution to contact resistance from the channel access region and confirms significant improvement through less damaging metallization techniques (i.e., reduced scattering) combined with strongly scaled HKMG stacks (enhanced carrier density). A clean contact/channel interface is achieved through high-vacuum evaporation and temperature-controlled stepped deposition providing large improvements in contact resistance. Our study reports low contact resistance of 5.7 kΩ-µm, with on-state currents of ~ 97 µA/µm and subthreshold swing of ~ 140 mV/dec in FETs with channel lengths of 400 nm. Furthermore, theoretical analysis using a Landauer transport ballistic model for WSe2SB-FETs elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance (excellent on-state current vs subthreshold swing benchmarks) towards the ultimate CMOS scaling limit.
more »
« less
- PAR ID:
- 10399172
- Publisher / Repository:
- Nature Publishing Group
- Date Published:
- Journal Name:
- Scientific Reports
- Volume:
- 13
- Issue:
- 1
- ISSN:
- 2045-2322
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
More Like this
-
-
Abstract 2D layered semiconductors have attracted considerable attention for beyond‐Si complementary metal‐oxide‐semiconductor (CMOS) technologies. They can be prepared into ultrathin channel materials toward ultrascaled device architectures, including double‐gate field‐effect‐transistors (DGFETs). This work presents an experimental analysis of DGFETs constructed from chemical vapor deposition (CVD)‐grown monolayer (1L) molybdenum disulfide (MoS2) with atomic layer deposition (ALD) of hafnium oxide (HfO2) high‐k gate dielectrics (top and bottom). This extends beyond previous studies of DGFETs based mostly on exfoliated (few‐nm thick) MoS2flakes, and advances toward large‐area wafer‐scale processing. Here, significant improvements in performance are obtained with DGFETs (i.e., improvements in ON/OFF ratio, ON‐state current, sub‐threshold swing, etc.) compared to single top‐gate FETs. In addition to multi‐gate device architectures (e.g., DGFETs), the scaling of the equivalent oxide thickness (EOT) is crucial toward improved electrostatics required for next‐generation transistors. However, the impact of EOT scaling on the characteristics of CVD‐grown MoS2DGFETs remains largely unexplored. Thus, this work studies the impact of EOT scaling on subthreshold swing (SS) and gate hysteresis using current–voltage (I–V) measurements with varying sweep rates. The experimental analysis and results elucidate the basic mechanisms responsible for improvements in CVD‐grown 1L‐MoS2DGFETs compared to standard top‐gate FETs.more » « less
-
Abstract We report threshold voltage (VTH) control in ultrawide bandgap Al0.4Ga0.6N-channel metal oxide semiconductor heterostructure field-effect transistors using a high-temperature (300 °C) anneal of the high-kZrO2gate-insulator. Annealing switched the polarity of the fixed charges at the ZrO2/AlGaN interface from +5.5 × 1013cm−2to −4.2 × 1013cm−2, pinningVTHat ∼ (−12 V), reducing gate leakage by ∼103, and improving subthreshold swing 2× (116 mV decade−1). It also enabled the gate to repeatedly withstand voltages from −40 to +18 V, allowing the channel to be overdriven doubling the peak currents to ∼0.5 A mm−1.more » « less
-
Abstract Faux‐hawk fullerenes are promising candidates for high‐performance organic field‐effect transistors (OFETs). They show dense molecular packing and high thermal stability. Furthermore, in contrast to most other C60derivates, functionalization of the fullerene core by the fluorinated group C6F4CF2does not increase their lowest unoccupied orbital position, which allows the use of air‐stable molecular n‐dopants to optimize their performance. The influence of n‐doping on the performance of OFETs based on the faux‐hawk fullerene 1,9‐C60(cyclo‐CF2(2‐C6F4)) (C60FHF) is studied. An analytic model for n‐doped transistors is presented and used to clarify the origin of the increase in the subthreshold swing usually observed in doped OFETs. It is shown that the increase in subthreshold swing can be minimized by using a bulk dopant layer at the gate dielectric/C60FHF layer instead of a mixed host:dopant layer. Following an optimization of the OFETs, an average electron mobility of 0.34 cm2 V−1 s−1, a subthreshold swing below 400 mV dec−1for doped transistors, and a contact resistance of 10 kΩ cm is obtained, which is among the best performance for fullerene based n‐type semiconductors.more » « less
-
null (Ed.)High contact resistance is one of the primary concerns for electronic device applications of two-dimensional (2D) layered semiconductors. Here, we explore the enhanced carrier transport through metal–semiconductor interfaces in WS 2 field effect transistors (FETs) by introducing a typical transition metal, Cu, with two different doping strategies: (i) a “generalized” Cu doping by using randomly distributed Cu atoms along the channel and (ii) a “localized” Cu doping by adapting an ultrathin Cu layer at the metal–semiconductor interface. Compared to the pristine WS 2 FETs, both the generalized Cu atomic dopant and localized Cu contact decoration can provide a Schottky-to-Ohmic contact transition owing to the reduced contact resistances by 1–3 orders of magnitude, and consequently elevate electron mobilities by 5–7 times. Our work demonstrates that the introduction of transition metal can be an efficient and reliable technique to enhance the carrier transport and device performance in 2D TMD FETs.more » « less
