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III-Nitride light-emitting diodes (LEDs) and laser diodes (LDs) are light sources covering ultraviolet (UV) and visible spectral regimes, which offer benefits including compact size, wavelength tuning, long lifetime, and sustainability. UV light sources have a range of applications in the fields of biology and medicine, such as sterilization and the purification of both water and air, where visible light emitters have been used in miniaturized photonic devices for optogenetic applications and other light-based therapies. Those III-Nitride light sources provide tremendous potential to be integrated with silicon (Si)-based lab-on-a-chip (LOC) technology, which typically requires the coupling of an external light source through fiber optic cable, limiting the field deployment of the devices. Integrating an on-chip III-Nitride light source with these devices opens the door to complete LOC technology, allowing for the simultaneous detection of multiple bio agents on a single platform without the need for external photonic sources. While most integrated microsystems still rely on wafer bonding at the device or wafer level, one promising method to achieve the integration of III-nitride UV and visible LEDs and LDs with conventional Si photonics and complementary metal-oxide-semiconductor (CMOS) platforms is through the use of micro-transfer printing (µTP). µTP has greater tolerances in alignment than techniques such as flip-chip integration and allows for the transfer of many devices at once. Additionally, the µTP process does not call for the complex and high temperature processing required for standard wafer bonding or necessitate complicated growth and lattice matching needed for monolithic integration. To enable µTP, an elastomeric, such as polydimethylsiloxane (PDMS), is utilized to create a transfer stamp that is employed for the precise selection of fabricated semiconductor devices for transfer from a source wafer to a target wafer. III-Nitride LEDs or LDs epitaxial structures are grown on a source wafer and fabricated through the creation of tethered coupons, or individual devices. This is accomplished by utilizing III-nitride materials grown on (111) Si. These devices can be fabricated through standard lithography and etching processes, etching down to the (111) Si substrate. A larger mesa can be patterned and etched into the Si substrate, exposing the sidewalls for wet chemical etching. The finished devices are then encapsulated in SiNxthrough plasma enhanced chemical vapor deposition (PECVD), which is patterned through standard lithography to define tethers and anchors for the subsequent wet etch. The fabricated devices are oriented in such a way as to take advantage of the difference in etch rates (>100x) of Si(110) and Si(111) in potassium hydroxide (KOH), where etching proceeds along the <110> direction. After KOH etching, the devices are left encapsulated in SiNxand suspended over the silicon substrate with an air gap, while the anchors and tethers are left largely unaffected.This enables the elastomer stamp to press down, breaking the tethers, and releasing the device. The stamp is then able to transfer the device to a target wafer that has been coated and patterned with InterVia, a spin-on dielectric material that acts as an adhesion layer. The stamp is pressed into the target wafer in such a way that the device is adhered to the target and released from the elastomer stamp. This technique can be applied to LEDs and LDs grown on (111) Si, allowing for the heterogeneous integration of III-nitride LED and LDs with conventional CMOS and Si photonic integrated circuits (PICs) as on-chip light sources, opening the door to complete LOC technology without the need for additional external photonic sources.
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Deposition-last lithographically defined epitaxial complex oxide devices on Si(100)
The epitaxial growth of SrTiO 3 on Si(100) substrates that have been lithographically patterned to realize deposition-last, lithographically defined oxide devices on Si is explored. In contrast to traditional deposition-last techniques which create a physical hard mask on top of the substrate prior to epitaxial growth, a pseudomask is instead created by texturing the Si substrate surface itself. The Si is textured through a combination of reactive ion etching and wet-etching using a tetramethylammonium hydroxide solution. Desorbing the native SiO x at high temperatures prior to epitaxial growth in ultrahigh vacuum presents no complications as the patterned substrate is comprised entirely of Si. The inverted profile in which the epitaxial oxide device layer is above the textured pseudomask circumvents shadowing during deposition associated with conventional hard masks, thereby opening a pathway for highly scaled devices to be created.
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- PAR ID:
- 10418866
- Date Published:
- Journal Name:
- Journal of Vacuum Science & Technology A
- Volume:
- 40
- Issue:
- 5
- ISSN:
- 0734-2101
- Page Range / eLocation ID:
- 052701
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
-
Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.1116/6.0001939
